3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
7 * Marvell Semiconductor <www.marvell.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/armada100.h>
33 #include <asm/arch/utmi-armada100.h>
35 static int utmi_phy_init(void)
37 struct armd1usb_phy_reg *phy_regs =
38 (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
41 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
43 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
45 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
46 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
48 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
52 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
58 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
60 clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
63 setbits_le32(&phy_regs->utmi_tx, RCAL_START);
65 clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
68 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
77 * Initialize USB host controller's UTMI Physical interface
81 struct armd1mpmu_registers *mpmu_regs =
82 (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
84 struct armd1apmu_registers *apmu_regs =
85 (struct armd1apmu_registers *)ARMD1_APMU_BASE;
87 /* Turn on 26Mhz ref clock for UTMI PLL */
88 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
91 writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
92 writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
94 /* Initialize UTMI transceiver */
95 return utmi_phy_init();