git.sur5r.net Git - u-boot/blob - drivers/usb/host/xhci-dwc3.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * DWC3 controller driver
   5  *
   6  * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <fdtdec.h>
  14 #include <generic-phy.h>
  15 #include <usb.h>
  16
  17 #include "xhci.h"
  18 #include <asm/io.h>
  19 #include <linux/usb/dwc3.h>
  20 #include <linux/usb/otg.h>
  21
  22 struct xhci_dwc3_platdata {
  23         struct phy *usb_phys;
  24         int num_phys;
  25 };
  26
  27 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
  28 {
  29         clrsetbits_le32(&dwc3_reg->g_ctl,
  30                         DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
  31                         DWC3_GCTL_PRTCAPDIR(mode));
  32 }
  33
  34 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
  35 {
  36         /* Assert USB3 PHY reset */
  37         setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  38
  39         /* Assert USB2 PHY reset */
  40         setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  41
  42         mdelay(100);
  43
  44         /* Clear USB3 PHY reset */
  45         clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  46
  47         /* Clear USB2 PHY reset */
  48         clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  49 }
  50
  51 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
  52 {
  53         /* Before Resetting PHY, put Core in Reset */
  54         setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  55
  56         /* reset USB3 phy - if required */
  57         dwc3_phy_reset(dwc3_reg);
  58
  59         mdelay(100);
  60
  61         /* After PHYs are stable we can take Core out of reset state */
  62         clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  63 }
  64
  65 int dwc3_core_init(struct dwc3 *dwc3_reg)
  66 {
  67         u32 reg;
  68         u32 revision;
  69         unsigned int dwc3_hwparams1;
  70
  71         revision = readl(&dwc3_reg->g_snpsid);
  72         /* This should read as U3 followed by revision number */
  73         if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
  74                 puts("this is not a DesignWare USB3 DRD Core\n");
  75                 return -1;
  76         }
  77
  78         dwc3_core_soft_reset(dwc3_reg);
  79
  80         dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
  81
  82         reg = readl(&dwc3_reg->g_ctl);
  83         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  84         reg &= ~DWC3_GCTL_DISSCRAMBLE;
  85         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
  86         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  87                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  88                 break;
  89         default:
  90                 debug("No power optimization available\n");
  91         }
  92
  93         /*
  94          * WORKAROUND: DWC3 revisions <1.90a have a bug
  95          * where the device can fail to connect at SuperSpeed
  96          * and falls back to high-speed mode which causes
  97          * the device to enter a Connect/Disconnect loop
  98          */
  99         if ((revision & DWC3_REVISION_MASK) < 0x190a)
 100                 reg |= DWC3_GCTL_U2RSTECN;
 101
 102         writel(reg, &dwc3_reg->g_ctl);
 103
 104         return 0;
 105 }
 106
 107 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 108 {
 109         setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
 110                         GFLADJ_30MHZ(val));
 111 }
 112
 113 #ifdef CONFIG_DM_USB
 114 static int xhci_dwc3_setup_phy(struct udevice *dev)
 115 {
 116         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 117         int i, ret, count;
 118
 119         /* Return if no phy declared */
 120         if (!dev_read_prop(dev, "phys", NULL))
 121                 return 0;
 122
 123         count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
 124         if (count <= 0)
 125                 return count;
 126
 127         plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
 128                                       GFP_KERNEL);
 129         if (!plat->usb_phys)
 130                 return -ENOMEM;
 131
 132         for (i = 0; i < count; i++) {
 133                 ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]);
 134                 if (ret && ret != -ENOENT) {
 135                         pr_err("Failed to get USB PHY%d for %s\n",
 136                                i, dev->name);
 137                         return ret;
 138                 }
 139
 140                 ++plat->num_phys;
 141         }
 142
 143         for (i = 0; i < plat->num_phys; i++) {
 144                 ret = generic_phy_init(&plat->usb_phys[i]);
 145                 if (ret) {
 146                         pr_err("Can't init USB PHY%d for %s\n",
 147                                i, dev->name);
 148                         goto phys_init_err;
 149                 }
 150         }
 151
 152         for (i = 0; i < plat->num_phys; i++) {
 153                 ret = generic_phy_power_on(&plat->usb_phys[i]);
 154                 if (ret) {
 155                         pr_err("Can't power USB PHY%d for %s\n",
 156                                i, dev->name);
 157                         goto phys_poweron_err;
 158                 }
 159         }
 160
 161         return 0;
 162
 163 phys_poweron_err:
 164         for (; i >= 0; i--)
 165                 generic_phy_power_off(&plat->usb_phys[i]);
 166
 167         for (i = 0; i < plat->num_phys; i++)
 168                 generic_phy_exit(&plat->usb_phys[i]);
 169
 170         return ret;
 171
 172 phys_init_err:
 173         for (; i >= 0; i--)
 174                 generic_phy_exit(&plat->usb_phys[i]);
 175
 176         return ret;
 177 }
 178
 179 static int xhci_dwc3_shutdown_phy(struct udevice *dev)
 180 {
 181         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 182         int i, ret;
 183
 184         for (i = 0; i < plat->num_phys; i++) {
 185                 if (!generic_phy_valid(&plat->usb_phys[i]))
 186                         continue;
 187
 188                 ret = generic_phy_power_off(&plat->usb_phys[i]);
 189                 ret |= generic_phy_exit(&plat->usb_phys[i]);
 190                 if (ret) {
 191                         pr_err("Can't shutdown USB PHY%d for %s\n",
 192                                i, dev->name);
 193                 }
 194         }
 195
 196         return 0;
 197 }
 198
 199 static int xhci_dwc3_probe(struct udevice *dev)
 200 {
 201         struct xhci_hcor *hcor;
 202         struct xhci_hccr *hccr;
 203         struct dwc3 *dwc3_reg;
 204         enum usb_dr_mode dr_mode;
 205         int ret;
 206
 207         hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
 208         hcor = (struct xhci_hcor *)((uintptr_t)hccr +
 209                         HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 210
 211         ret = xhci_dwc3_setup_phy(dev);
 212         if (ret)
 213                 return ret;
 214
 215         dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
 216
 217         dwc3_core_init(dwc3_reg);
 218
 219         dr_mode = usb_get_dr_mode(dev_of_offset(dev));
 220         if (dr_mode == USB_DR_MODE_UNKNOWN)
 221                 /* by default set dual role mode to HOST */
 222                 dr_mode = USB_DR_MODE_HOST;
 223
 224         dwc3_set_mode(dwc3_reg, dr_mode);
 225
 226         return xhci_register(dev, hccr, hcor);
 227 }
 228
 229 static int xhci_dwc3_remove(struct udevice *dev)
 230 {
 231         xhci_dwc3_shutdown_phy(dev);
 232
 233         return xhci_deregister(dev);
 234 }
 235
 236 static const struct udevice_id xhci_dwc3_ids[] = {
 237         { .compatible = "snps,dwc3" },
 238         { }
 239 };
 240
 241 U_BOOT_DRIVER(xhci_dwc3) = {
 242         .name = "xhci-dwc3",
 243         .id = UCLASS_USB,
 244         .of_match = xhci_dwc3_ids,
 245         .probe = xhci_dwc3_probe,
 246         .remove = xhci_dwc3_remove,
 247         .ops = &xhci_usb_ops,
 248         .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
 249         .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
 250         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 251 };
 252 #endif