2 * OMAP USB HOST xHCI Controller
5 * Texas Instruments, <www.ti.com>
7 * Author: Dan Murphy <dmurphy@ti.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm-generic/errno.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/sys_proto.h>
19 #include <linux/compat.h>
20 #include <linux/usb/dwc3.h>
21 #include <linux/usb/xhci-omap.h>
25 /* Declare global data pointer */
26 DECLARE_GLOBAL_DATA_PTR;
28 static struct omap_xhci omap;
30 struct usb_dpll_params {
38 #define NUM_USB_CLKS 6
40 static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
41 {1250, 5, 4, 20, 0}, /* 12 MHz */
42 {3125, 20, 4, 20, 0}, /* 16.8 MHz */
43 {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
44 {1250, 12, 4, 20, 0}, /* 26 MHz */
45 {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
46 {1000, 7, 4, 10, 0}, /* 20 MHz */
49 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
53 writel(SET_PLL_GO, &phy_regs->pll_go);
55 val = readl(&phy_regs->pll_status);
61 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
63 u32 clk_index = get_sys_clk_index();
66 val = readl(&phy_regs->pll_config_1);
67 val &= ~PLL_REGN_MASK;
68 val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
69 writel(val, &phy_regs->pll_config_1);
71 val = readl(&phy_regs->pll_config_2);
72 val &= ~PLL_SELFREQDCO_MASK;
73 val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
74 writel(val, &phy_regs->pll_config_2);
76 val = readl(&phy_regs->pll_config_1);
77 val &= ~PLL_REGM_MASK;
78 val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
79 writel(val, &phy_regs->pll_config_1);
81 val = readl(&phy_regs->pll_config_4);
82 val &= ~PLL_REGM_F_MASK;
83 val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
84 writel(val, &phy_regs->pll_config_4);
86 val = readl(&phy_regs->pll_config_3);
88 val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
89 writel(val, &phy_regs->pll_config_3);
91 omap_usb_dpll_relock(phy_regs);
94 static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
96 u32 rate = get_sys_clk_freq()/1000000;
99 val = readl((*ctrl)->control_phy_power_usb);
100 val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
101 val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
102 val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
104 writel(val, (*ctrl)->control_phy_power_usb);
107 static void usb3_phy_power(int on)
111 val = readl((*ctrl)->control_phy_power_usb);
113 val &= ~USB3_PWRCTL_CLK_CMD_MASK;
114 val |= USB3_PHY_TX_RX_POWERON;
116 val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
119 writel(val, (*ctrl)->control_phy_power_usb);
122 static void dwc_usb3_phy_init(struct omap_usb3_phy *phy_regs)
124 omap_usb_dpll_lock(phy_regs);
126 usb3_phy_partial_powerup(phy_regs);
128 * Give enough time for the PHY to partially power-up before
129 * powering it up completely. delay value suggested by the HW
136 static void omap_enable_phy_clocks(struct omap_xhci *omap)
140 /* Setting OCP2SCP1 register */
141 setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
142 OCP2SCP1_CLKCTRL_MODULEMODE_HW);
144 /* Turn on 32K AON clk */
145 setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
146 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
148 /* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
149 writel(0x0, (*prcm)->cm_l3init_clkstctrl);
151 val = (USBOTGSS_DMADISABLE |
152 USBOTGSS_STANDBYMODE_SMRT_WKUP |
153 USBOTGSS_IDLEMODE_NOIDLE);
154 writel(val, &omap->otg_wrapper->sysconfig);
156 /* Clear the utmi OTG status */
157 val = readl(&omap->otg_wrapper->utmi_otg_status);
158 writel(val, &omap->otg_wrapper->utmi_otg_status);
160 /* Enable interrupts */
161 writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
162 val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
163 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
164 USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN |
165 USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN |
166 USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN |
167 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN |
168 USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
169 USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
170 USBOTGSS_IRQ_SET_1_OEVT_EN);
171 writel(val, &omap->otg_wrapper->irqenable_set_1);
173 /* Clear the IRQ status */
174 val = readl(&omap->otg_wrapper->irqstatus_1);
175 writel(val, &omap->otg_wrapper->irqstatus_1);
176 val = readl(&omap->otg_wrapper->irqstatus_0);
177 writel(val, &omap->otg_wrapper->irqstatus_0);
179 /* Enable the USB OTG Super speed clocks */
180 val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
181 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
185 inline int __board_usb_init(int index, enum board_usb_init_type init)
189 int board_usb_init(int index, enum board_usb_init_type init) \
190 __attribute__((weak, alias("__board_usb_init")));
192 static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
194 clrsetbits_le32(&dwc3_reg->g_ctl,
195 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
196 DWC3_GCTL_PRTCAPDIR(mode));
199 static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
201 /* Before Resetting PHY, put Core in Reset */
202 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
204 /* Assert USB3 PHY reset */
205 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
207 /* Assert USB2 PHY reset */
208 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
212 /* Clear USB3 PHY reset */
213 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
215 /* Clear USB2 PHY reset */
216 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
218 /* After PHYs are stable we can take Core out of reset state */
219 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
222 static int dwc3_core_init(struct dwc3 *dwc3_reg)
226 unsigned int dwc3_hwparams1;
228 revision = readl(&dwc3_reg->g_snpsid);
229 /* This should read as U3 followed by revision number */
230 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
231 puts("this is not a DesignWare USB3 DRD Core\n");
235 dwc3_core_soft_reset(dwc3_reg);
237 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
239 reg = readl(&dwc3_reg->g_ctl);
240 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
241 reg &= ~DWC3_GCTL_DISSCRAMBLE;
242 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
243 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
244 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
247 debug("No power optimization available\n");
251 * WORKAROUND: DWC3 revisions <1.90a have a bug
252 * where the device can fail to connect at SuperSpeed
253 * and falls back to high-speed mode which causes
254 * the device to enter a Connect/Disconnect loop
256 if ((revision & DWC3_REVISION_MASK) < 0x190a)
257 reg |= DWC3_GCTL_U2RSTECN;
259 writel(reg, &dwc3_reg->g_ctl);
264 static int omap_xhci_core_init(struct omap_xhci *omap)
268 omap_enable_phy_clocks(omap);
270 dwc_usb3_phy_init(omap->usb3_phy);
272 ret = dwc3_core_init(omap->dwc3_reg);
274 debug("%s:failed to initialize core\n", __func__);
278 /* We are hard-coding DWC3 core to Host Mode */
279 dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
284 static void omap_xhci_core_exit(struct omap_xhci *omap)
289 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
291 struct omap_xhci *ctx = &omap;
294 ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
295 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
296 ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
297 ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
299 ret = board_usb_init(index, USB_INIT_HOST);
301 puts("Failed to initialize board for USB\n");
305 ret = omap_xhci_core_init(ctx);
307 puts("Failed to initialize xhci\n");
311 *hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
312 *hcor = (struct xhci_hcor *)((uint32_t) *hccr
313 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
315 debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
316 (uint32_t)*hccr, (uint32_t)*hcor,
317 (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
322 void xhci_hcd_stop(int index)
324 struct omap_xhci *ctx = &omap;
326 omap_xhci_core_exit(ctx);