2 * Copyright (c) 2016 Rockchip, Inc.
3 * Authors: Daniel Meng <daniel.meng@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <linux/errno.h>
16 #include <linux/compat.h>
17 #include <linux/usb/dwc3.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 struct rockchip_xhci_platdata {
26 struct gpio_desc vbus_gpio;
30 * Contains pointers to register base addresses
31 * for the usb controller.
33 struct rockchip_xhci {
34 struct usb_platdata usb_plat;
35 struct xhci_ctrl ctrl;
36 struct xhci_hccr *hcd;
37 struct dwc3 *dwc3_reg;
40 static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
42 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
43 struct udevice *child;
47 * Get the base address for XHCI controller from the device node
49 plat->hcd_base = dev_get_addr(dev);
50 if (plat->hcd_base == FDT_ADDR_T_NONE) {
51 debug("Can't get the XHCI register base address\n");
55 /* Get the base address for usbphy from the device node */
56 for (device_find_first_child(dev, &child); child;
57 device_find_next_child(&child)) {
58 if (!of_device_is_compatible(child, "rockchip,rk3399-usb3-phy"))
60 plat->phy_base = dev_get_addr(child);
64 if (plat->phy_base == FDT_ADDR_T_NONE) {
65 debug("Can't get the usbphy register address\n");
70 ret = gpio_request_by_name(dev, "rockchip,vbus-gpio", 0,
71 &plat->vbus_gpio, GPIOD_IS_OUT);
73 debug("rockchip,vbus-gpio node missing!");
79 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
80 * @dwc: Pointer to our controller context structure
81 * @dev: Pointer to ulcass device
83 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
87 const void *blob = gd->fdt_blob;
90 /* Set dwc3 usb2 phy config */
91 reg = readl(&dwc3_reg->g_usb2phycfg[0]);
93 if (fdtdec_get_bool(blob, dev_of_offset(dev),
94 "snps,dis-enblslpm-quirk"))
95 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
97 utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev),
98 "snps,phyif-utmi-bits", -1);
99 if (utmi_bits == 16) {
100 reg |= DWC3_GUSB2PHYCFG_PHYIF;
101 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
102 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
103 } else if (utmi_bits == 8) {
104 reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
105 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
106 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
109 if (fdtdec_get_bool(blob, dev_of_offset(dev),
110 "snps,dis-u2-freeclk-exists-quirk"))
111 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
113 if (fdtdec_get_bool(blob, dev_of_offset(dev),
114 "snps,dis-u2-susphy-quirk"))
115 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
117 writel(reg, &dwc3_reg->g_usb2phycfg[0]);
120 static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
125 ret = dwc3_core_init(rkxhci->dwc3_reg);
127 debug("failed to initialize core\n");
131 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
133 /* We are hard-coding DWC3 core to Host Mode */
134 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
139 static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
144 static int xhci_usb_probe(struct udevice *dev)
146 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
147 struct rockchip_xhci *ctx = dev_get_priv(dev);
148 struct xhci_hcor *hcor;
151 ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
152 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
153 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
154 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
156 /* setup the Vbus gpio here */
157 if (dm_gpio_is_valid(&plat->vbus_gpio))
158 dm_gpio_set_value(&plat->vbus_gpio, 1);
160 ret = rockchip_xhci_core_init(ctx, dev);
162 debug("XHCI: failed to initialize controller\n");
166 return xhci_register(dev, ctx->hcd, hcor);
169 static int xhci_usb_remove(struct udevice *dev)
171 struct rockchip_xhci *ctx = dev_get_priv(dev);
174 ret = xhci_deregister(dev);
177 ret = rockchip_xhci_core_exit(ctx);
184 static const struct udevice_id xhci_usb_ids[] = {
185 { .compatible = "rockchip,rk3399-xhci" },
189 U_BOOT_DRIVER(usb_xhci) = {
190 .name = "xhci_rockchip",
192 .of_match = xhci_usb_ids,
193 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
194 .probe = xhci_usb_probe,
195 .remove = xhci_usb_remove,
196 .ops = &xhci_usb_ops,
197 .bind = dm_scan_fdt_dev,
198 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
199 .priv_auto_alloc_size = sizeof(struct rockchip_xhci),
200 .flags = DM_FLAG_ALLOC_PRIV_DMA,
203 static const struct udevice_id usb_phy_ids[] = {
204 { .compatible = "rockchip,rk3399-usb3-phy" },
208 U_BOOT_DRIVER(usb_phy) = {
209 .name = "usb_phy_rockchip",
210 .of_match = usb_phy_ids,