1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip, Inc.
4 * Authors: Daniel Meng <daniel.meng@rock-chips.com>
11 #include <linux/errno.h>
12 #include <linux/compat.h>
13 #include <linux/usb/dwc3.h>
14 #include <power/regulator.h>
18 struct rockchip_xhci_platdata {
21 struct udevice *vbus_supply;
25 * Contains pointers to register base addresses
26 * for the usb controller.
28 struct rockchip_xhci {
29 struct usb_platdata usb_plat;
30 struct xhci_ctrl ctrl;
31 struct xhci_hccr *hcd;
32 struct dwc3 *dwc3_reg;
35 static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
37 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
38 struct udevice *child;
42 * Get the base address for XHCI controller from the device node
44 plat->hcd_base = dev_read_addr(dev);
45 if (plat->hcd_base == FDT_ADDR_T_NONE) {
46 pr_err("Can't get the XHCI register base address\n");
50 /* Get the base address for usbphy from the device node */
51 for (device_find_first_child(dev, &child); child;
52 device_find_next_child(&child)) {
53 if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy"))
55 plat->phy_base = devfdt_get_addr(child);
59 if (plat->phy_base == FDT_ADDR_T_NONE) {
60 pr_err("Can't get the usbphy register address\n");
65 ret = device_get_supply_regulator(dev, "vbus-supply",
68 debug("Can't get VBus regulator!\n");
74 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
75 * @dwc: Pointer to our controller context structure
76 * @dev: Pointer to ulcass device
78 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
84 /* Set dwc3 usb2 phy config */
85 reg = readl(&dwc3_reg->g_usb2phycfg[0]);
87 if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
88 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
90 utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
91 if (utmi_bits == 16) {
92 reg |= DWC3_GUSB2PHYCFG_PHYIF;
93 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
94 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
95 } else if (utmi_bits == 8) {
96 reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
97 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
98 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
101 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
102 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
104 if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
105 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
107 writel(reg, &dwc3_reg->g_usb2phycfg[0]);
110 static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
115 ret = dwc3_core_init(rkxhci->dwc3_reg);
117 pr_err("failed to initialize core\n");
121 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
123 /* We are hard-coding DWC3 core to Host Mode */
124 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
129 static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
134 static int xhci_usb_probe(struct udevice *dev)
136 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
137 struct rockchip_xhci *ctx = dev_get_priv(dev);
138 struct xhci_hcor *hcor;
141 ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
142 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
143 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
144 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
146 if (plat->vbus_supply) {
147 ret = regulator_set_enable(plat->vbus_supply, true);
149 pr_err("XHCI: failed to set VBus supply\n");
154 ret = rockchip_xhci_core_init(ctx, dev);
156 pr_err("XHCI: failed to initialize controller\n");
160 return xhci_register(dev, ctx->hcd, hcor);
163 static int xhci_usb_remove(struct udevice *dev)
165 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
166 struct rockchip_xhci *ctx = dev_get_priv(dev);
169 ret = xhci_deregister(dev);
172 ret = rockchip_xhci_core_exit(ctx);
176 if (plat->vbus_supply) {
177 ret = regulator_set_enable(plat->vbus_supply, false);
179 pr_err("XHCI: failed to set VBus supply\n");
185 static const struct udevice_id xhci_usb_ids[] = {
186 { .compatible = "rockchip,rk3399-xhci" },
187 { .compatible = "rockchip,rk3328-xhci" },
191 U_BOOT_DRIVER(usb_xhci) = {
192 .name = "xhci_rockchip",
194 .of_match = xhci_usb_ids,
195 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
196 .probe = xhci_usb_probe,
197 .remove = xhci_usb_remove,
198 .ops = &xhci_usb_ops,
199 .bind = dm_scan_fdt_dev,
200 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
201 .priv_auto_alloc_size = sizeof(struct rockchip_xhci),
202 .flags = DM_FLAG_ALLOC_PRIV_DMA,
205 static const struct udevice_id usb_phy_ids[] = {
206 { .compatible = "rockchip,rk3399-usb3-phy" },
207 { .compatible = "rockchip,rk3328-usb3-phy" },
211 U_BOOT_DRIVER(usb_phy) = {
212 .name = "usb_phy_rockchip",
213 .of_match = usb_phy_ids,