2 * Mentor USB OTG Core host controller driver.
4 * Copyright (c) 2008 Texas Instruments
6 * SPDX-License-Identifier: GPL-2.0+
8 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
15 /* MSC control transfers */
16 #define USB_MSC_BBB_RESET 0xFF
17 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
19 /* Endpoint configuration information */
20 static const struct musb_epinfo epinfo[3] = {
21 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
22 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
23 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
26 /* --- Virtual Root Hub ---------------------------------------------------- */
27 #ifdef MUSB_NO_MULTIPOINT
29 static u32 port_status;
31 #include <usbroothubdes.h>
36 * This function writes the data toggle value.
38 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
40 u16 toggle = usb_gettoggle(dev, ep, dir_out);
44 csr = readw(&musbr->txcsr);
46 if (csr & MUSB_TXCSR_MODE)
47 csr = MUSB_TXCSR_CLRDATATOG;
50 writew(csr, &musbr->txcsr);
52 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
53 writew(csr, &musbr->txcsr);
54 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
55 writew(csr, &musbr->txcsr);
59 csr = readw(&musbr->txcsr);
60 if (csr & MUSB_TXCSR_MODE)
61 csr = MUSB_RXCSR_CLRDATATOG;
64 writew(csr, &musbr->rxcsr);
66 csr = readw(&musbr->rxcsr);
67 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
68 writew(csr, &musbr->rxcsr);
69 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
70 writew(csr, &musbr->rxcsr);
76 * This function checks if RxStall has occured on the endpoint. If a RxStall
77 * has occured, the RxStall is cleared and 1 is returned. If RxStall has
78 * not occured, 0 is returned.
80 static u8 check_stall(u8 ep, u8 dir_out)
86 csr = readw(&musbr->txcsr);
87 if (csr & MUSB_CSR0_H_RXSTALL) {
88 csr &= ~MUSB_CSR0_H_RXSTALL;
89 writew(csr, &musbr->txcsr);
92 } else { /* For non-ep0 */
93 if (dir_out) { /* is it tx ep */
94 csr = readw(&musbr->txcsr);
95 if (csr & MUSB_TXCSR_H_RXSTALL) {
96 csr &= ~MUSB_TXCSR_H_RXSTALL;
97 writew(csr, &musbr->txcsr);
100 } else { /* is it rx ep */
101 csr = readw(&musbr->rxcsr);
102 if (csr & MUSB_RXCSR_H_RXSTALL) {
103 csr &= ~MUSB_RXCSR_H_RXSTALL;
104 writew(csr, &musbr->rxcsr);
113 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
114 * error and -2 for stall.
116 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
120 int timeout = CONFIG_MUSB_TIMEOUT;
123 csr = readw(&musbr->txcsr);
124 if (csr & MUSB_CSR0_H_ERROR) {
125 csr &= ~MUSB_CSR0_H_ERROR;
126 writew(csr, &musbr->txcsr);
127 dev->status = USB_ST_CRC_ERR;
133 case MUSB_CSR0_TXPKTRDY:
134 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
135 if (check_stall(MUSB_CONTROL_EP, 0)) {
136 dev->status = USB_ST_STALLED;
143 case MUSB_CSR0_RXPKTRDY:
144 if (check_stall(MUSB_CONTROL_EP, 0)) {
145 dev->status = USB_ST_STALLED;
148 if (csr & MUSB_CSR0_RXPKTRDY)
152 case MUSB_CSR0_H_REQPKT:
153 if (!(csr & MUSB_CSR0_H_REQPKT)) {
154 if (check_stall(MUSB_CONTROL_EP, 0)) {
155 dev->status = USB_ST_STALLED;
163 /* Check the timeout */
167 dev->status = USB_ST_CRC_ERR;
177 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
179 static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
182 int timeout = CONFIG_MUSB_TIMEOUT;
185 if (check_stall(ep, 1)) {
186 dev->status = USB_ST_STALLED;
190 csr = readw(&musbr->txcsr);
191 if (csr & MUSB_TXCSR_H_ERROR) {
192 dev->status = USB_ST_CRC_ERR;
196 /* Check the timeout */
200 dev->status = USB_ST_CRC_ERR;
204 } while (csr & MUSB_TXCSR_TXPKTRDY);
209 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
211 static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
214 int timeout = CONFIG_MUSB_TIMEOUT;
217 if (check_stall(ep, 0)) {
218 dev->status = USB_ST_STALLED;
222 csr = readw(&musbr->rxcsr);
223 if (csr & MUSB_RXCSR_H_ERROR) {
224 dev->status = USB_ST_CRC_ERR;
228 /* Check the timeout */
232 dev->status = USB_ST_CRC_ERR;
236 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
241 * This function performs the setup phase of the control transfer
243 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
248 /* write the control request to ep0 fifo */
249 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
251 /* enable transfer of setup packet */
252 csr = readw(&musbr->txcsr);
253 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
254 writew(csr, &musbr->txcsr);
256 /* wait until the setup packet is transmitted */
257 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
263 * This function handles the control transfer in data phase
265 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
270 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
271 u8 *rxbuff = (u8 *)buffer;
275 while (rxlen < len) {
276 /* Determine the next read length */
277 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
279 /* Set the ReqPkt bit */
280 csr = readw(&musbr->txcsr);
281 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
282 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
286 /* Actual number of bytes received by usb */
287 rxedlength = readb(&musbr->rxcount);
289 /* Read the data from the RxFIFO */
290 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
292 /* Clear the RxPktRdy Bit */
293 csr = readw(&musbr->txcsr);
294 csr &= ~MUSB_CSR0_RXPKTRDY;
295 writew(csr, &musbr->txcsr);
298 if (rxedlength != nextlen) {
299 dev->act_len += rxedlength;
303 dev->act_len = rxlen;
309 * This function handles the control transfer out data phase
311 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
316 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
317 u8 *txbuff = (u8 *)buffer;
320 while (txlen < len) {
321 /* Determine the next write length */
322 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
324 /* Load the data to send in FIFO */
325 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
327 /* Set TXPKTRDY bit */
328 csr = readw(&musbr->txcsr);
330 csr |= MUSB_CSR0_TXPKTRDY;
331 #if !defined(CONFIG_SOC_DM365)
332 csr |= MUSB_CSR0_H_DIS_PING;
334 writew(csr, &musbr->txcsr);
335 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
340 dev->act_len = txlen;
346 * This function handles the control transfer out status phase
348 static int ctrlreq_out_status_phase(struct usb_device *dev)
353 /* Set the StatusPkt bit */
354 csr = readw(&musbr->txcsr);
355 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
356 #if !defined(CONFIG_SOC_DM365)
357 csr |= MUSB_CSR0_H_DIS_PING;
359 writew(csr, &musbr->txcsr);
361 /* Wait until TXPKTRDY bit is cleared */
362 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
367 * This function handles the control transfer in status phase
369 static int ctrlreq_in_status_phase(struct usb_device *dev)
374 /* Set the StatusPkt bit and ReqPkt bit */
375 csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
376 #if !defined(CONFIG_SOC_DM365)
377 csr |= MUSB_CSR0_H_DIS_PING;
379 writew(csr, &musbr->txcsr);
380 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
382 /* clear StatusPkt bit and RxPktRdy bit */
383 csr = readw(&musbr->txcsr);
384 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
385 writew(csr, &musbr->txcsr);
390 * determines the speed of the device (High/Full/Slow)
392 static u8 get_dev_speed(struct usb_device *dev)
394 return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
395 ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
396 MUSB_TYPE_SPEED_FULL);
400 * configure the hub address and the port address.
402 static void config_hub_port(struct usb_device *dev, u8 ep)
407 /* Find out the nearest parent which is high speed */
408 while (dev->parent->parent != NULL)
409 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
414 /* determine the port address at that hub */
415 hub = dev->parent->devnum;
416 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
417 if (dev->parent->children[chid] == dev)
420 #ifndef MUSB_NO_MULTIPOINT
421 /* configure the hub address and the port address */
422 writeb(hub, &musbr->tar[ep].txhubaddr);
423 writeb((chid + 1), &musbr->tar[ep].txhubport);
424 writeb(hub, &musbr->tar[ep].rxhubaddr);
425 writeb((chid + 1), &musbr->tar[ep].rxhubport);
429 #ifdef MUSB_NO_MULTIPOINT
431 static void musb_port_reset(int do_reset)
433 u8 power = readb(&musbr->power);
437 writeb(power | MUSB_POWER_RESET, &musbr->power);
438 port_status |= USB_PORT_STAT_RESET;
439 port_status &= ~USB_PORT_STAT_ENABLE;
442 writeb(power & ~MUSB_POWER_RESET, &musbr->power);
444 power = readb(&musbr->power);
445 if (power & MUSB_POWER_HSMODE)
446 port_status |= USB_PORT_STAT_HIGH_SPEED;
448 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
449 port_status |= USB_PORT_STAT_ENABLE
450 | (USB_PORT_STAT_C_RESET << 16)
451 | (USB_PORT_STAT_C_ENABLE << 16);
458 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
459 void *buffer, int transfer_len,
460 struct devrequest *cmd)
462 int leni = transfer_len;
466 const u8 *data_buf = (u8 *) datab;
473 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
474 debug("Root-Hub submit IRQ: NOT implemented\n");
478 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
479 wValue = swap_16(cmd->value);
480 wIndex = swap_16(cmd->index);
481 wLength = swap_16(cmd->length);
483 debug("--- HUB ----------------------------------------\n");
484 debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
485 bmRType_bReq, wValue, wIndex, wLength);
486 debug("------------------------------------------------\n");
488 switch (bmRType_bReq) {
490 debug("RH_GET_STATUS\n");
492 *(__u16 *) data_buf = swap_16(1);
496 case RH_GET_STATUS | RH_INTERFACE:
497 debug("RH_GET_STATUS | RH_INTERFACE\n");
499 *(__u16 *) data_buf = swap_16(0);
503 case RH_GET_STATUS | RH_ENDPOINT:
504 debug("RH_GET_STATUS | RH_ENDPOINT\n");
506 *(__u16 *) data_buf = swap_16(0);
510 case RH_GET_STATUS | RH_CLASS:
511 debug("RH_GET_STATUS | RH_CLASS\n");
513 *(__u32 *) data_buf = swap_32(0);
517 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
518 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
520 int_usb = readw(&musbr->intrusb);
521 if (int_usb & MUSB_INTR_CONNECT) {
522 port_status |= USB_PORT_STAT_CONNECTION
523 | (USB_PORT_STAT_C_CONNECTION << 16);
524 port_status |= USB_PORT_STAT_HIGH_SPEED
525 | USB_PORT_STAT_ENABLE;
528 if (port_status & USB_PORT_STAT_RESET)
531 *(__u32 *) data_buf = swap_32(port_status);
535 case RH_CLEAR_FEATURE | RH_ENDPOINT:
536 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
539 case RH_ENDPOINT_STALL:
540 debug("C_HUB_ENDPOINT_STALL\n");
544 port_status &= ~(1 << wValue);
547 case RH_CLEAR_FEATURE | RH_CLASS:
548 debug("RH_CLEAR_FEATURE | RH_CLASS\n");
551 case RH_C_HUB_LOCAL_POWER:
552 debug("C_HUB_LOCAL_POWER\n");
556 case RH_C_HUB_OVER_CURRENT:
557 debug("C_HUB_OVER_CURRENT\n");
561 port_status &= ~(1 << wValue);
564 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
565 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
572 case RH_PORT_SUSPEND:
580 case RH_C_PORT_CONNECTION:
584 case RH_C_PORT_ENABLE:
588 case RH_C_PORT_SUSPEND:
592 case RH_C_PORT_OVER_CURRENT:
596 case RH_C_PORT_RESET:
601 debug("invalid wValue\n");
602 stat = USB_ST_STALLED;
605 port_status &= ~(1 << wValue);
608 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
609 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
612 case RH_PORT_SUSPEND:
630 debug("invalid wValue\n");
631 stat = USB_ST_STALLED;
634 port_status |= 1 << wValue;
638 debug("RH_SET_ADDRESS\n");
644 case RH_GET_DESCRIPTOR:
645 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
648 case (USB_DT_DEVICE << 8): /* device descriptor */
649 len = min_t(unsigned int,
650 leni, min_t(unsigned int,
651 sizeof(root_hub_dev_des),
653 data_buf = root_hub_dev_des;
656 case (USB_DT_CONFIG << 8): /* configuration descriptor */
657 len = min_t(unsigned int,
658 leni, min_t(unsigned int,
659 sizeof(root_hub_config_des),
661 data_buf = root_hub_config_des;
664 case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
665 len = min_t(unsigned int,
666 leni, min_t(unsigned int,
667 sizeof(root_hub_str_index0),
669 data_buf = root_hub_str_index0;
672 case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
673 len = min_t(unsigned int,
674 leni, min_t(unsigned int,
675 sizeof(root_hub_str_index1),
677 data_buf = root_hub_str_index1;
681 debug("invalid wValue\n");
682 stat = USB_ST_STALLED;
687 case RH_GET_DESCRIPTOR | RH_CLASS: {
688 u8 *_data_buf = (u8 *) datab;
689 debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
691 _data_buf[0] = 0x09; /* min length; */
693 _data_buf[2] = 0x1; /* 1 port */
694 _data_buf[3] = 0x01; /* per-port power switching */
695 _data_buf[3] |= 0x10; /* no overcurrent reporting */
697 /* Corresponds to data_buf[4-7] */
704 len = min_t(unsigned int, leni,
705 min_t(unsigned int, data_buf[0], wLength));
709 case RH_GET_CONFIGURATION:
710 debug("RH_GET_CONFIGURATION\n");
712 *(__u8 *) data_buf = 0x01;
716 case RH_SET_CONFIGURATION:
717 debug("RH_SET_CONFIGURATION\n");
723 debug("*** *** *** unsupported root hub command *** *** ***\n");
724 stat = USB_ST_STALLED;
727 len = min_t(int, len, leni);
728 if (buffer != data_buf)
729 memcpy(buffer, data_buf, len);
733 debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
738 static void musb_rh_init(void)
746 static void musb_rh_init(void) {}
751 * do a control transfer
753 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
754 int len, struct devrequest *setup)
756 int devnum = usb_pipedevice(pipe);
759 #ifdef MUSB_NO_MULTIPOINT
760 /* Control message is for the HUB? */
761 if (devnum == rh_devnum) {
762 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
768 /* select control endpoint */
769 writeb(MUSB_CONTROL_EP, &musbr->index);
770 readw(&musbr->txcsr);
772 #ifndef MUSB_NO_MULTIPOINT
773 /* target addr and (for multipoint) hub addr/port */
774 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
775 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
778 /* configure the hub address and the port number as required */
779 devspeed = get_dev_speed(dev);
780 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
781 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
782 config_hub_port(dev, MUSB_CONTROL_EP);
783 writeb(devspeed << 6, &musbr->txtype);
785 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
786 #ifndef MUSB_NO_MULTIPOINT
787 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
788 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
789 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
790 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
794 /* Control transfer setup phase */
795 if (ctrlreq_setup_phase(dev, setup) < 0)
798 switch (setup->request) {
799 case USB_REQ_GET_DESCRIPTOR:
800 case USB_REQ_GET_CONFIGURATION:
801 case USB_REQ_GET_INTERFACE:
802 case USB_REQ_GET_STATUS:
803 case USB_MSC_BBB_GET_MAX_LUN:
804 /* control transfer in-data-phase */
805 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
807 /* control transfer out-status-phase */
808 if (ctrlreq_out_status_phase(dev) < 0)
812 case USB_REQ_SET_ADDRESS:
813 case USB_REQ_SET_CONFIGURATION:
814 case USB_REQ_SET_FEATURE:
815 case USB_REQ_SET_INTERFACE:
816 case USB_REQ_CLEAR_FEATURE:
817 case USB_MSC_BBB_RESET:
818 /* control transfer in status phase */
819 if (ctrlreq_in_status_phase(dev) < 0)
823 case USB_REQ_SET_DESCRIPTOR:
824 /* control transfer out data phase */
825 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
827 /* control transfer in status phase */
828 if (ctrlreq_in_status_phase(dev) < 0)
833 /* unhandled control transfer */
840 #ifdef MUSB_NO_MULTIPOINT
841 /* Set device address to USB_FADDR register */
842 if (setup->request == USB_REQ_SET_ADDRESS)
843 writeb(dev->devnum, &musbr->faddr);
852 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
853 void *buffer, int len)
855 int dir_out = usb_pipeout(pipe);
856 int ep = usb_pipeendpoint(pipe);
857 #ifndef MUSB_NO_MULTIPOINT
858 int devnum = usb_pipedevice(pipe);
866 /* select bulk endpoint */
867 writeb(MUSB_BULK_EP, &musbr->index);
869 #ifndef MUSB_NO_MULTIPOINT
870 /* write the address of the device */
872 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
874 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
877 /* configure the hub address and the port number as required */
878 devspeed = get_dev_speed(dev);
879 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
880 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
882 * MUSB is in high speed and the destination device is full
883 * speed device. So configure the hub address and port
886 config_hub_port(dev, MUSB_BULK_EP);
888 #ifndef MUSB_NO_MULTIPOINT
890 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
891 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
893 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
894 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
897 devspeed = musb_cfg.musb_speed;
900 /* Write the saved toggle bit value */
901 write_toggle(dev, ep, dir_out);
903 if (dir_out) { /* bulk-out transfer */
904 /* Program the TxType register */
905 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
906 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
907 (ep & MUSB_TYPE_REMOTE_END);
908 writeb(type, &musbr->txtype);
910 /* Write maximum packet size to the TxMaxp register */
911 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
912 while (txlen < len) {
913 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
914 (len-txlen) : dev->epmaxpacketout[ep];
916 #ifdef CONFIG_USB_BLACKFIN
917 /* Set the transfer data size */
918 writew(nextlen, &musbr->txcount);
921 /* Write the data to the FIFO */
922 write_fifo(MUSB_BULK_EP, nextlen,
923 (void *)(((u8 *)buffer) + txlen));
925 /* Set the TxPktRdy bit */
926 csr = readw(&musbr->txcsr);
927 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
929 /* Wait until the TxPktRdy bit is cleared */
930 if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
931 readw(&musbr->txcsr);
932 usb_settoggle(dev, ep, dir_out,
933 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
934 dev->act_len = txlen;
940 /* Keep a copy of the data toggle bit */
941 csr = readw(&musbr->txcsr);
942 usb_settoggle(dev, ep, dir_out,
943 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
944 } else { /* bulk-in transfer */
945 /* Write the saved toggle bit value */
946 write_toggle(dev, ep, dir_out);
948 /* Program the RxType register */
949 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
950 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
951 (ep & MUSB_TYPE_REMOTE_END);
952 writeb(type, &musbr->rxtype);
954 /* Write the maximum packet size to the RxMaxp register */
955 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
956 while (txlen < len) {
957 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
958 (len-txlen) : dev->epmaxpacketin[ep];
960 /* Set the ReqPkt bit */
961 csr = readw(&musbr->rxcsr);
962 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
964 /* Wait until the RxPktRdy bit is set */
965 if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
966 csr = readw(&musbr->rxcsr);
967 usb_settoggle(dev, ep, dir_out,
968 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
969 csr &= ~MUSB_RXCSR_RXPKTRDY;
970 writew(csr, &musbr->rxcsr);
971 dev->act_len = txlen;
975 /* Read the data from the FIFO */
976 read_fifo(MUSB_BULK_EP, nextlen,
977 (void *)(((u8 *)buffer) + txlen));
979 /* Clear the RxPktRdy bit */
980 csr = readw(&musbr->rxcsr);
981 csr &= ~MUSB_RXCSR_RXPKTRDY;
982 writew(csr, &musbr->rxcsr);
986 /* Keep a copy of the data toggle bit */
987 csr = readw(&musbr->rxcsr);
988 usb_settoggle(dev, ep, dir_out,
989 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
992 /* bulk transfer is complete */
999 * This function initializes the usb controller module.
1001 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1008 if (musb_platform_init() == -1)
1011 /* Configure all the endpoint FIFO's and start usb controller */
1012 musbr = musb_cfg.regs;
1013 musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1017 * Wait until musb is enabled in host mode with a timeout. There
1018 * should be a usb device connected.
1020 timeout = musb_cfg.timeout;
1022 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1025 /* if musb core is not in host mode, then return */
1029 /* start usb bus reset */
1030 power = readb(&musbr->power);
1031 writeb(power | MUSB_POWER_RESET, &musbr->power);
1033 /* After initiating a usb reset, wait for about 20ms to 30ms */
1036 /* stop usb bus reset */
1037 power = readb(&musbr->power);
1038 power &= ~MUSB_POWER_RESET;
1039 writeb(power, &musbr->power);
1041 /* Determine if the connected device is a high/full/low speed device */
1042 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1043 MUSB_TYPE_SPEED_HIGH :
1044 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1045 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1050 * This function stops the operation of the davinci usb module.
1052 int usb_lowlevel_stop(int index)
1054 /* Reset the USB module */
1055 musb_platform_deinit();
1056 writeb(0, &musbr->devctl);
1061 * This function supports usb interrupt transfers. Currently, usb interrupt
1062 * transfers are not supported.
1064 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1065 void *buffer, int len, int interval)
1067 int dir_out = usb_pipeout(pipe);
1068 int ep = usb_pipeendpoint(pipe);
1069 #ifndef MUSB_NO_MULTIPOINT
1070 int devnum = usb_pipedevice(pipe);
1078 /* select interrupt endpoint */
1079 writeb(MUSB_INTR_EP, &musbr->index);
1081 #ifndef MUSB_NO_MULTIPOINT
1082 /* write the address of the device */
1084 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1086 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1089 /* configure the hub address and the port number as required */
1090 devspeed = get_dev_speed(dev);
1091 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1092 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
1094 * MUSB is in high speed and the destination device is full
1095 * speed device. So configure the hub address and port
1096 * address registers.
1098 config_hub_port(dev, MUSB_INTR_EP);
1100 #ifndef MUSB_NO_MULTIPOINT
1102 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1103 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1105 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1106 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1109 devspeed = musb_cfg.musb_speed;
1112 /* Write the saved toggle bit value */
1113 write_toggle(dev, ep, dir_out);
1115 if (!dir_out) { /* intrrupt-in transfer */
1116 /* Write the saved toggle bit value */
1117 write_toggle(dev, ep, dir_out);
1118 writeb(interval, &musbr->rxinterval);
1120 /* Program the RxType register */
1121 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1122 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1123 (ep & MUSB_TYPE_REMOTE_END);
1124 writeb(type, &musbr->rxtype);
1126 /* Write the maximum packet size to the RxMaxp register */
1127 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1129 while (txlen < len) {
1130 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1131 (len-txlen) : dev->epmaxpacketin[ep];
1133 /* Set the ReqPkt bit */
1134 csr = readw(&musbr->rxcsr);
1135 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1137 /* Wait until the RxPktRdy bit is set */
1138 if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
1139 csr = readw(&musbr->rxcsr);
1140 usb_settoggle(dev, ep, dir_out,
1141 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1142 csr &= ~MUSB_RXCSR_RXPKTRDY;
1143 writew(csr, &musbr->rxcsr);
1144 dev->act_len = txlen;
1148 /* Read the data from the FIFO */
1149 read_fifo(MUSB_INTR_EP, nextlen,
1150 (void *)(((u8 *)buffer) + txlen));
1152 /* Clear the RxPktRdy bit */
1153 csr = readw(&musbr->rxcsr);
1154 csr &= ~MUSB_RXCSR_RXPKTRDY;
1155 writew(csr, &musbr->rxcsr);
1159 /* Keep a copy of the data toggle bit */
1160 csr = readw(&musbr->rxcsr);
1161 usb_settoggle(dev, ep, dir_out,
1162 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1165 /* interrupt transfer is complete */
1166 dev->irq_status = 0;
1167 dev->irq_act_len = len;
1168 dev->irq_handle(dev);