2 * Mentor USB OTG Core host controller driver.
4 * Copyright (c) 2008 Texas Instruments
6 * SPDX-License-Identifier: GPL-2.0+
8 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
15 /* MSC control transfers */
16 #define USB_MSC_BBB_RESET 0xFF
17 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
19 /* Endpoint configuration information */
20 static const struct musb_epinfo epinfo[3] = {
21 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
22 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
23 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
26 /* --- Virtual Root Hub ---------------------------------------------------- */
27 #ifdef MUSB_NO_MULTIPOINT
29 static u32 port_status;
31 /* Device descriptor */
32 static const u8 root_hub_dev_des[] = {
33 0x12, /* __u8 bLength; */
34 0x01, /* __u8 bDescriptorType; Device */
35 0x00, /* __u16 bcdUSB; v1.1 */
37 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
38 0x00, /* __u8 bDeviceSubClass; */
39 0x00, /* __u8 bDeviceProtocol; */
40 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
41 0x00, /* __u16 idVendor; */
43 0x00, /* __u16 idProduct; */
45 0x00, /* __u16 bcdDevice; */
47 0x00, /* __u8 iManufacturer; */
48 0x01, /* __u8 iProduct; */
49 0x00, /* __u8 iSerialNumber; */
50 0x01 /* __u8 bNumConfigurations; */
53 /* Configuration descriptor */
54 static const u8 root_hub_config_des[] = {
55 0x09, /* __u8 bLength; */
56 0x02, /* __u8 bDescriptorType; Configuration */
57 0x19, /* __u16 wTotalLength; */
59 0x01, /* __u8 bNumInterfaces; */
60 0x01, /* __u8 bConfigurationValue; */
61 0x00, /* __u8 iConfiguration; */
62 0x40, /* __u8 bmAttributes;
63 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
64 0x00, /* __u8 MaxPower; */
67 0x09, /* __u8 if_bLength; */
68 0x04, /* __u8 if_bDescriptorType; Interface */
69 0x00, /* __u8 if_bInterfaceNumber; */
70 0x00, /* __u8 if_bAlternateSetting; */
71 0x01, /* __u8 if_bNumEndpoints; */
72 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
73 0x00, /* __u8 if_bInterfaceSubClass; */
74 0x00, /* __u8 if_bInterfaceProtocol; */
75 0x00, /* __u8 if_iInterface; */
78 0x07, /* __u8 ep_bLength; */
79 0x05, /* __u8 ep_bDescriptorType; Endpoint */
80 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
81 0x03, /* __u8 ep_bmAttributes; Interrupt */
82 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
84 0xff /* __u8 ep_bInterval; 255 ms */
87 static const unsigned char root_hub_str_index0[] = {
88 0x04, /* __u8 bLength; */
89 0x03, /* __u8 bDescriptorType; String-descriptor */
90 0x09, /* __u8 lang ID */
91 0x04, /* __u8 lang ID */
94 static const unsigned char root_hub_str_index1[] = {
95 0x1c, /* __u8 bLength; */
96 0x03, /* __u8 bDescriptorType; String-descriptor */
97 'M', /* __u8 Unicode */
99 'U', /* __u8 Unicode */
100 0, /* __u8 Unicode */
101 'S', /* __u8 Unicode */
102 0, /* __u8 Unicode */
103 'B', /* __u8 Unicode */
104 0, /* __u8 Unicode */
105 ' ', /* __u8 Unicode */
106 0, /* __u8 Unicode */
107 'R', /* __u8 Unicode */
108 0, /* __u8 Unicode */
109 'o', /* __u8 Unicode */
110 0, /* __u8 Unicode */
111 'o', /* __u8 Unicode */
112 0, /* __u8 Unicode */
113 't', /* __u8 Unicode */
114 0, /* __u8 Unicode */
115 ' ', /* __u8 Unicode */
116 0, /* __u8 Unicode */
117 'H', /* __u8 Unicode */
118 0, /* __u8 Unicode */
119 'u', /* __u8 Unicode */
120 0, /* __u8 Unicode */
121 'b', /* __u8 Unicode */
122 0, /* __u8 Unicode */
127 * This function writes the data toggle value.
129 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
131 u16 toggle = usb_gettoggle(dev, ep, dir_out);
135 csr = readw(&musbr->txcsr);
137 if (csr & MUSB_TXCSR_MODE)
138 csr = MUSB_TXCSR_CLRDATATOG;
141 writew(csr, &musbr->txcsr);
143 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
144 writew(csr, &musbr->txcsr);
145 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
146 writew(csr, &musbr->txcsr);
150 csr = readw(&musbr->txcsr);
151 if (csr & MUSB_TXCSR_MODE)
152 csr = MUSB_RXCSR_CLRDATATOG;
155 writew(csr, &musbr->rxcsr);
157 csr = readw(&musbr->rxcsr);
158 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
159 writew(csr, &musbr->rxcsr);
160 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
161 writew(csr, &musbr->rxcsr);
167 * This function checks if RxStall has occured on the endpoint. If a RxStall
168 * has occured, the RxStall is cleared and 1 is returned. If RxStall has
169 * not occured, 0 is returned.
171 static u8 check_stall(u8 ep, u8 dir_out)
177 csr = readw(&musbr->txcsr);
178 if (csr & MUSB_CSR0_H_RXSTALL) {
179 csr &= ~MUSB_CSR0_H_RXSTALL;
180 writew(csr, &musbr->txcsr);
183 } else { /* For non-ep0 */
184 if (dir_out) { /* is it tx ep */
185 csr = readw(&musbr->txcsr);
186 if (csr & MUSB_TXCSR_H_RXSTALL) {
187 csr &= ~MUSB_TXCSR_H_RXSTALL;
188 writew(csr, &musbr->txcsr);
191 } else { /* is it rx ep */
192 csr = readw(&musbr->rxcsr);
193 if (csr & MUSB_RXCSR_H_RXSTALL) {
194 csr &= ~MUSB_RXCSR_H_RXSTALL;
195 writew(csr, &musbr->rxcsr);
204 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
205 * error and -2 for stall.
207 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
211 int timeout = CONFIG_MUSB_TIMEOUT;
214 csr = readw(&musbr->txcsr);
215 if (csr & MUSB_CSR0_H_ERROR) {
216 csr &= ~MUSB_CSR0_H_ERROR;
217 writew(csr, &musbr->txcsr);
218 dev->status = USB_ST_CRC_ERR;
224 case MUSB_CSR0_TXPKTRDY:
225 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
226 if (check_stall(MUSB_CONTROL_EP, 0)) {
227 dev->status = USB_ST_STALLED;
234 case MUSB_CSR0_RXPKTRDY:
235 if (check_stall(MUSB_CONTROL_EP, 0)) {
236 dev->status = USB_ST_STALLED;
239 if (csr & MUSB_CSR0_RXPKTRDY)
243 case MUSB_CSR0_H_REQPKT:
244 if (!(csr & MUSB_CSR0_H_REQPKT)) {
245 if (check_stall(MUSB_CONTROL_EP, 0)) {
246 dev->status = USB_ST_STALLED;
254 /* Check the timeout */
258 dev->status = USB_ST_CRC_ERR;
268 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
270 static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
273 int timeout = CONFIG_MUSB_TIMEOUT;
276 if (check_stall(ep, 1)) {
277 dev->status = USB_ST_STALLED;
281 csr = readw(&musbr->txcsr);
282 if (csr & MUSB_TXCSR_H_ERROR) {
283 dev->status = USB_ST_CRC_ERR;
287 /* Check the timeout */
291 dev->status = USB_ST_CRC_ERR;
295 } while (csr & MUSB_TXCSR_TXPKTRDY);
300 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
302 static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
305 int timeout = CONFIG_MUSB_TIMEOUT;
308 if (check_stall(ep, 0)) {
309 dev->status = USB_ST_STALLED;
313 csr = readw(&musbr->rxcsr);
314 if (csr & MUSB_RXCSR_H_ERROR) {
315 dev->status = USB_ST_CRC_ERR;
319 /* Check the timeout */
323 dev->status = USB_ST_CRC_ERR;
327 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
332 * This function performs the setup phase of the control transfer
334 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
339 /* write the control request to ep0 fifo */
340 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
342 /* enable transfer of setup packet */
343 csr = readw(&musbr->txcsr);
344 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
345 writew(csr, &musbr->txcsr);
347 /* wait until the setup packet is transmitted */
348 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
354 * This function handles the control transfer in data phase
356 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
361 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
362 u8 *rxbuff = (u8 *)buffer;
366 while (rxlen < len) {
367 /* Determine the next read length */
368 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
370 /* Set the ReqPkt bit */
371 csr = readw(&musbr->txcsr);
372 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
373 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
377 /* Actual number of bytes received by usb */
378 rxedlength = readb(&musbr->rxcount);
380 /* Read the data from the RxFIFO */
381 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
383 /* Clear the RxPktRdy Bit */
384 csr = readw(&musbr->txcsr);
385 csr &= ~MUSB_CSR0_RXPKTRDY;
386 writew(csr, &musbr->txcsr);
389 if (rxedlength != nextlen) {
390 dev->act_len += rxedlength;
394 dev->act_len = rxlen;
400 * This function handles the control transfer out data phase
402 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
407 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
408 u8 *txbuff = (u8 *)buffer;
411 while (txlen < len) {
412 /* Determine the next write length */
413 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
415 /* Load the data to send in FIFO */
416 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
418 /* Set TXPKTRDY bit */
419 csr = readw(&musbr->txcsr);
421 csr |= MUSB_CSR0_TXPKTRDY;
422 #if !defined(CONFIG_SOC_DM365)
423 csr |= MUSB_CSR0_H_DIS_PING;
425 writew(csr, &musbr->txcsr);
426 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
431 dev->act_len = txlen;
437 * This function handles the control transfer out status phase
439 static int ctrlreq_out_status_phase(struct usb_device *dev)
444 /* Set the StatusPkt bit */
445 csr = readw(&musbr->txcsr);
446 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
447 #if !defined(CONFIG_SOC_DM365)
448 csr |= MUSB_CSR0_H_DIS_PING;
450 writew(csr, &musbr->txcsr);
452 /* Wait until TXPKTRDY bit is cleared */
453 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
458 * This function handles the control transfer in status phase
460 static int ctrlreq_in_status_phase(struct usb_device *dev)
465 /* Set the StatusPkt bit and ReqPkt bit */
466 csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
467 #if !defined(CONFIG_SOC_DM365)
468 csr |= MUSB_CSR0_H_DIS_PING;
470 writew(csr, &musbr->txcsr);
471 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
473 /* clear StatusPkt bit and RxPktRdy bit */
474 csr = readw(&musbr->txcsr);
475 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
476 writew(csr, &musbr->txcsr);
481 * determines the speed of the device (High/Full/Slow)
483 static u8 get_dev_speed(struct usb_device *dev)
485 return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
486 ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
487 MUSB_TYPE_SPEED_FULL);
491 * configure the hub address and the port address.
493 static void config_hub_port(struct usb_device *dev, u8 ep)
498 /* Find out the nearest parent which is high speed */
499 while (dev->parent->parent != NULL)
500 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
505 /* determine the port address at that hub */
506 hub = dev->parent->devnum;
507 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
508 if (dev->parent->children[chid] == dev)
511 #ifndef MUSB_NO_MULTIPOINT
512 /* configure the hub address and the port address */
513 writeb(hub, &musbr->tar[ep].txhubaddr);
514 writeb((chid + 1), &musbr->tar[ep].txhubport);
515 writeb(hub, &musbr->tar[ep].rxhubaddr);
516 writeb((chid + 1), &musbr->tar[ep].rxhubport);
520 #ifdef MUSB_NO_MULTIPOINT
522 static void musb_port_reset(int do_reset)
524 u8 power = readb(&musbr->power);
528 writeb(power | MUSB_POWER_RESET, &musbr->power);
529 port_status |= USB_PORT_STAT_RESET;
530 port_status &= ~USB_PORT_STAT_ENABLE;
533 writeb(power & ~MUSB_POWER_RESET, &musbr->power);
535 power = readb(&musbr->power);
536 if (power & MUSB_POWER_HSMODE)
537 port_status |= USB_PORT_STAT_HIGH_SPEED;
539 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
540 port_status |= USB_PORT_STAT_ENABLE
541 | (USB_PORT_STAT_C_RESET << 16)
542 | (USB_PORT_STAT_C_ENABLE << 16);
549 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
550 void *buffer, int transfer_len,
551 struct devrequest *cmd)
553 int leni = transfer_len;
557 const u8 *data_buf = (u8 *) datab;
564 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
565 debug("Root-Hub submit IRQ: NOT implemented\n");
569 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
570 wValue = swap_16(cmd->value);
571 wIndex = swap_16(cmd->index);
572 wLength = swap_16(cmd->length);
574 debug("--- HUB ----------------------------------------\n");
575 debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
576 bmRType_bReq, wValue, wIndex, wLength);
577 debug("------------------------------------------------\n");
579 switch (bmRType_bReq) {
581 debug("RH_GET_STATUS\n");
583 *(__u16 *) data_buf = swap_16(1);
587 case RH_GET_STATUS | RH_INTERFACE:
588 debug("RH_GET_STATUS | RH_INTERFACE\n");
590 *(__u16 *) data_buf = swap_16(0);
594 case RH_GET_STATUS | RH_ENDPOINT:
595 debug("RH_GET_STATUS | RH_ENDPOINT\n");
597 *(__u16 *) data_buf = swap_16(0);
601 case RH_GET_STATUS | RH_CLASS:
602 debug("RH_GET_STATUS | RH_CLASS\n");
604 *(__u32 *) data_buf = swap_32(0);
608 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
609 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
611 int_usb = readw(&musbr->intrusb);
612 if (int_usb & MUSB_INTR_CONNECT) {
613 port_status |= USB_PORT_STAT_CONNECTION
614 | (USB_PORT_STAT_C_CONNECTION << 16);
615 port_status |= USB_PORT_STAT_HIGH_SPEED
616 | USB_PORT_STAT_ENABLE;
619 if (port_status & USB_PORT_STAT_RESET)
622 *(__u32 *) data_buf = swap_32(port_status);
626 case RH_CLEAR_FEATURE | RH_ENDPOINT:
627 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
630 case RH_ENDPOINT_STALL:
631 debug("C_HUB_ENDPOINT_STALL\n");
635 port_status &= ~(1 << wValue);
638 case RH_CLEAR_FEATURE | RH_CLASS:
639 debug("RH_CLEAR_FEATURE | RH_CLASS\n");
642 case RH_C_HUB_LOCAL_POWER:
643 debug("C_HUB_LOCAL_POWER\n");
647 case RH_C_HUB_OVER_CURRENT:
648 debug("C_HUB_OVER_CURRENT\n");
652 port_status &= ~(1 << wValue);
655 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
656 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
663 case RH_PORT_SUSPEND:
671 case RH_C_PORT_CONNECTION:
675 case RH_C_PORT_ENABLE:
679 case RH_C_PORT_SUSPEND:
683 case RH_C_PORT_OVER_CURRENT:
687 case RH_C_PORT_RESET:
692 debug("invalid wValue\n");
693 stat = USB_ST_STALLED;
696 port_status &= ~(1 << wValue);
699 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
700 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
703 case RH_PORT_SUSPEND:
721 debug("invalid wValue\n");
722 stat = USB_ST_STALLED;
725 port_status |= 1 << wValue;
729 debug("RH_SET_ADDRESS\n");
735 case RH_GET_DESCRIPTOR:
736 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
739 case (USB_DT_DEVICE << 8): /* device descriptor */
740 len = min_t(unsigned int,
741 leni, min_t(unsigned int,
742 sizeof(root_hub_dev_des),
744 data_buf = root_hub_dev_des;
747 case (USB_DT_CONFIG << 8): /* configuration descriptor */
748 len = min_t(unsigned int,
749 leni, min_t(unsigned int,
750 sizeof(root_hub_config_des),
752 data_buf = root_hub_config_des;
755 case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
756 len = min_t(unsigned int,
757 leni, min_t(unsigned int,
758 sizeof(root_hub_str_index0),
760 data_buf = root_hub_str_index0;
763 case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
764 len = min_t(unsigned int,
765 leni, min_t(unsigned int,
766 sizeof(root_hub_str_index1),
768 data_buf = root_hub_str_index1;
772 debug("invalid wValue\n");
773 stat = USB_ST_STALLED;
778 case RH_GET_DESCRIPTOR | RH_CLASS: {
779 u8 *_data_buf = (u8 *) datab;
780 debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
782 _data_buf[0] = 0x09; /* min length; */
784 _data_buf[2] = 0x1; /* 1 port */
785 _data_buf[3] = 0x01; /* per-port power switching */
786 _data_buf[3] |= 0x10; /* no overcurrent reporting */
788 /* Corresponds to data_buf[4-7] */
795 len = min_t(unsigned int, leni,
796 min_t(unsigned int, data_buf[0], wLength));
800 case RH_GET_CONFIGURATION:
801 debug("RH_GET_CONFIGURATION\n");
803 *(__u8 *) data_buf = 0x01;
807 case RH_SET_CONFIGURATION:
808 debug("RH_SET_CONFIGURATION\n");
814 debug("*** *** *** unsupported root hub command *** *** ***\n");
815 stat = USB_ST_STALLED;
818 len = min_t(int, len, leni);
819 if (buffer != data_buf)
820 memcpy(buffer, data_buf, len);
824 debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
829 static void musb_rh_init(void)
837 static void musb_rh_init(void) {}
842 * do a control transfer
844 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
845 int len, struct devrequest *setup)
847 int devnum = usb_pipedevice(pipe);
850 #ifdef MUSB_NO_MULTIPOINT
851 /* Control message is for the HUB? */
852 if (devnum == rh_devnum) {
853 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
859 /* select control endpoint */
860 writeb(MUSB_CONTROL_EP, &musbr->index);
861 readw(&musbr->txcsr);
863 #ifndef MUSB_NO_MULTIPOINT
864 /* target addr and (for multipoint) hub addr/port */
865 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
866 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
869 /* configure the hub address and the port number as required */
870 devspeed = get_dev_speed(dev);
871 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
872 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
873 config_hub_port(dev, MUSB_CONTROL_EP);
874 writeb(devspeed << 6, &musbr->txtype);
876 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
877 #ifndef MUSB_NO_MULTIPOINT
878 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
879 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
880 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
881 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
885 /* Control transfer setup phase */
886 if (ctrlreq_setup_phase(dev, setup) < 0)
889 switch (setup->request) {
890 case USB_REQ_GET_DESCRIPTOR:
891 case USB_REQ_GET_CONFIGURATION:
892 case USB_REQ_GET_INTERFACE:
893 case USB_REQ_GET_STATUS:
894 case USB_MSC_BBB_GET_MAX_LUN:
895 /* control transfer in-data-phase */
896 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
898 /* control transfer out-status-phase */
899 if (ctrlreq_out_status_phase(dev) < 0)
903 case USB_REQ_SET_ADDRESS:
904 case USB_REQ_SET_CONFIGURATION:
905 case USB_REQ_SET_FEATURE:
906 case USB_REQ_SET_INTERFACE:
907 case USB_REQ_CLEAR_FEATURE:
908 case USB_MSC_BBB_RESET:
909 /* control transfer in status phase */
910 if (ctrlreq_in_status_phase(dev) < 0)
914 case USB_REQ_SET_DESCRIPTOR:
915 /* control transfer out data phase */
916 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
918 /* control transfer in status phase */
919 if (ctrlreq_in_status_phase(dev) < 0)
924 /* unhandled control transfer */
931 #ifdef MUSB_NO_MULTIPOINT
932 /* Set device address to USB_FADDR register */
933 if (setup->request == USB_REQ_SET_ADDRESS)
934 writeb(dev->devnum, &musbr->faddr);
943 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
944 void *buffer, int len)
946 int dir_out = usb_pipeout(pipe);
947 int ep = usb_pipeendpoint(pipe);
948 #ifndef MUSB_NO_MULTIPOINT
949 int devnum = usb_pipedevice(pipe);
957 /* select bulk endpoint */
958 writeb(MUSB_BULK_EP, &musbr->index);
960 #ifndef MUSB_NO_MULTIPOINT
961 /* write the address of the device */
963 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
965 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
968 /* configure the hub address and the port number as required */
969 devspeed = get_dev_speed(dev);
970 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
971 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
973 * MUSB is in high speed and the destination device is full
974 * speed device. So configure the hub address and port
977 config_hub_port(dev, MUSB_BULK_EP);
979 #ifndef MUSB_NO_MULTIPOINT
981 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
982 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
984 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
985 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
988 devspeed = musb_cfg.musb_speed;
991 /* Write the saved toggle bit value */
992 write_toggle(dev, ep, dir_out);
994 if (dir_out) { /* bulk-out transfer */
995 /* Program the TxType register */
996 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
997 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
998 (ep & MUSB_TYPE_REMOTE_END);
999 writeb(type, &musbr->txtype);
1001 /* Write maximum packet size to the TxMaxp register */
1002 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
1003 while (txlen < len) {
1004 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
1005 (len-txlen) : dev->epmaxpacketout[ep];
1007 #ifdef CONFIG_USB_BLACKFIN
1008 /* Set the transfer data size */
1009 writew(nextlen, &musbr->txcount);
1012 /* Write the data to the FIFO */
1013 write_fifo(MUSB_BULK_EP, nextlen,
1014 (void *)(((u8 *)buffer) + txlen));
1016 /* Set the TxPktRdy bit */
1017 csr = readw(&musbr->txcsr);
1018 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
1020 /* Wait until the TxPktRdy bit is cleared */
1021 if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
1022 readw(&musbr->txcsr);
1023 usb_settoggle(dev, ep, dir_out,
1024 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
1025 dev->act_len = txlen;
1031 /* Keep a copy of the data toggle bit */
1032 csr = readw(&musbr->txcsr);
1033 usb_settoggle(dev, ep, dir_out,
1034 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
1035 } else { /* bulk-in transfer */
1036 /* Write the saved toggle bit value */
1037 write_toggle(dev, ep, dir_out);
1039 /* Program the RxType register */
1040 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1041 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
1042 (ep & MUSB_TYPE_REMOTE_END);
1043 writeb(type, &musbr->rxtype);
1045 /* Write the maximum packet size to the RxMaxp register */
1046 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1047 while (txlen < len) {
1048 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1049 (len-txlen) : dev->epmaxpacketin[ep];
1051 /* Set the ReqPkt bit */
1052 csr = readw(&musbr->rxcsr);
1053 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1055 /* Wait until the RxPktRdy bit is set */
1056 if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
1057 csr = readw(&musbr->rxcsr);
1058 usb_settoggle(dev, ep, dir_out,
1059 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1060 csr &= ~MUSB_RXCSR_RXPKTRDY;
1061 writew(csr, &musbr->rxcsr);
1062 dev->act_len = txlen;
1066 /* Read the data from the FIFO */
1067 read_fifo(MUSB_BULK_EP, nextlen,
1068 (void *)(((u8 *)buffer) + txlen));
1070 /* Clear the RxPktRdy bit */
1071 csr = readw(&musbr->rxcsr);
1072 csr &= ~MUSB_RXCSR_RXPKTRDY;
1073 writew(csr, &musbr->rxcsr);
1077 /* Keep a copy of the data toggle bit */
1078 csr = readw(&musbr->rxcsr);
1079 usb_settoggle(dev, ep, dir_out,
1080 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1083 /* bulk transfer is complete */
1090 * This function initializes the usb controller module.
1092 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1099 if (musb_platform_init() == -1)
1102 /* Configure all the endpoint FIFO's and start usb controller */
1103 musbr = musb_cfg.regs;
1104 musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1108 * Wait until musb is enabled in host mode with a timeout. There
1109 * should be a usb device connected.
1111 timeout = musb_cfg.timeout;
1113 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1116 /* if musb core is not in host mode, then return */
1120 /* start usb bus reset */
1121 power = readb(&musbr->power);
1122 writeb(power | MUSB_POWER_RESET, &musbr->power);
1124 /* After initiating a usb reset, wait for about 20ms to 30ms */
1127 /* stop usb bus reset */
1128 power = readb(&musbr->power);
1129 power &= ~MUSB_POWER_RESET;
1130 writeb(power, &musbr->power);
1132 /* Determine if the connected device is a high/full/low speed device */
1133 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1134 MUSB_TYPE_SPEED_HIGH :
1135 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1136 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1141 * This function stops the operation of the davinci usb module.
1143 int usb_lowlevel_stop(int index)
1145 /* Reset the USB module */
1146 musb_platform_deinit();
1147 writeb(0, &musbr->devctl);
1152 * This function supports usb interrupt transfers. Currently, usb interrupt
1153 * transfers are not supported.
1155 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1156 void *buffer, int len, int interval)
1158 int dir_out = usb_pipeout(pipe);
1159 int ep = usb_pipeendpoint(pipe);
1160 #ifndef MUSB_NO_MULTIPOINT
1161 int devnum = usb_pipedevice(pipe);
1169 /* select interrupt endpoint */
1170 writeb(MUSB_INTR_EP, &musbr->index);
1172 #ifndef MUSB_NO_MULTIPOINT
1173 /* write the address of the device */
1175 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1177 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1180 /* configure the hub address and the port number as required */
1181 devspeed = get_dev_speed(dev);
1182 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1183 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
1185 * MUSB is in high speed and the destination device is full
1186 * speed device. So configure the hub address and port
1187 * address registers.
1189 config_hub_port(dev, MUSB_INTR_EP);
1191 #ifndef MUSB_NO_MULTIPOINT
1193 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1194 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1196 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1197 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1200 devspeed = musb_cfg.musb_speed;
1203 /* Write the saved toggle bit value */
1204 write_toggle(dev, ep, dir_out);
1206 if (!dir_out) { /* intrrupt-in transfer */
1207 /* Write the saved toggle bit value */
1208 write_toggle(dev, ep, dir_out);
1209 writeb(interval, &musbr->rxinterval);
1211 /* Program the RxType register */
1212 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1213 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1214 (ep & MUSB_TYPE_REMOTE_END);
1215 writeb(type, &musbr->rxtype);
1217 /* Write the maximum packet size to the RxMaxp register */
1218 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1220 while (txlen < len) {
1221 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1222 (len-txlen) : dev->epmaxpacketin[ep];
1224 /* Set the ReqPkt bit */
1225 csr = readw(&musbr->rxcsr);
1226 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1228 /* Wait until the RxPktRdy bit is set */
1229 if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
1230 csr = readw(&musbr->rxcsr);
1231 usb_settoggle(dev, ep, dir_out,
1232 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1233 csr &= ~MUSB_RXCSR_RXPKTRDY;
1234 writew(csr, &musbr->rxcsr);
1235 dev->act_len = txlen;
1239 /* Read the data from the FIFO */
1240 read_fifo(MUSB_INTR_EP, nextlen,
1241 (void *)(((u8 *)buffer) + txlen));
1243 /* Clear the RxPktRdy bit */
1244 csr = readw(&musbr->rxcsr);
1245 csr &= ~MUSB_RXCSR_RXPKTRDY;
1246 writew(csr, &musbr->rxcsr);
1250 /* Keep a copy of the data toggle bit */
1251 csr = readw(&musbr->rxcsr);
1252 usb_settoggle(dev, ep, dir_out,
1253 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1256 /* interrupt transfer is complete */
1257 dev->irq_status = 0;
1258 dev->irq_act_len = len;
1259 dev->irq_handle(dev);