2 * Mentor USB OTG Core host controller driver.
4 * Copyright (c) 2008 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
28 /* MSC control transfers */
29 #define USB_MSC_BBB_RESET 0xFF
30 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
32 /* Endpoint configuration information */
33 static const struct musb_epinfo epinfo[3] = {
34 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
35 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
36 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
39 /* --- Virtual Root Hub ---------------------------------------------------- */
40 #ifdef MUSB_NO_MULTIPOINT
42 static u32 port_status;
44 /* Device descriptor */
45 static const u8 root_hub_dev_des[] = {
46 0x12, /* __u8 bLength; */
47 0x01, /* __u8 bDescriptorType; Device */
48 0x00, /* __u16 bcdUSB; v1.1 */
50 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
51 0x00, /* __u8 bDeviceSubClass; */
52 0x00, /* __u8 bDeviceProtocol; */
53 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
54 0x00, /* __u16 idVendor; */
56 0x00, /* __u16 idProduct; */
58 0x00, /* __u16 bcdDevice; */
60 0x00, /* __u8 iManufacturer; */
61 0x01, /* __u8 iProduct; */
62 0x00, /* __u8 iSerialNumber; */
63 0x01 /* __u8 bNumConfigurations; */
66 /* Configuration descriptor */
67 static const u8 root_hub_config_des[] = {
68 0x09, /* __u8 bLength; */
69 0x02, /* __u8 bDescriptorType; Configuration */
70 0x19, /* __u16 wTotalLength; */
72 0x01, /* __u8 bNumInterfaces; */
73 0x01, /* __u8 bConfigurationValue; */
74 0x00, /* __u8 iConfiguration; */
75 0x40, /* __u8 bmAttributes;
76 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
77 0x00, /* __u8 MaxPower; */
80 0x09, /* __u8 if_bLength; */
81 0x04, /* __u8 if_bDescriptorType; Interface */
82 0x00, /* __u8 if_bInterfaceNumber; */
83 0x00, /* __u8 if_bAlternateSetting; */
84 0x01, /* __u8 if_bNumEndpoints; */
85 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
86 0x00, /* __u8 if_bInterfaceSubClass; */
87 0x00, /* __u8 if_bInterfaceProtocol; */
88 0x00, /* __u8 if_iInterface; */
91 0x07, /* __u8 ep_bLength; */
92 0x05, /* __u8 ep_bDescriptorType; Endpoint */
93 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
94 0x03, /* __u8 ep_bmAttributes; Interrupt */
95 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
97 0xff /* __u8 ep_bInterval; 255 ms */
100 static const unsigned char root_hub_str_index0[] = {
101 0x04, /* __u8 bLength; */
102 0x03, /* __u8 bDescriptorType; String-descriptor */
103 0x09, /* __u8 lang ID */
104 0x04, /* __u8 lang ID */
107 static const unsigned char root_hub_str_index1[] = {
108 0x1c, /* __u8 bLength; */
109 0x03, /* __u8 bDescriptorType; String-descriptor */
110 'M', /* __u8 Unicode */
111 0, /* __u8 Unicode */
112 'U', /* __u8 Unicode */
113 0, /* __u8 Unicode */
114 'S', /* __u8 Unicode */
115 0, /* __u8 Unicode */
116 'B', /* __u8 Unicode */
117 0, /* __u8 Unicode */
118 ' ', /* __u8 Unicode */
119 0, /* __u8 Unicode */
120 'R', /* __u8 Unicode */
121 0, /* __u8 Unicode */
122 'o', /* __u8 Unicode */
123 0, /* __u8 Unicode */
124 'o', /* __u8 Unicode */
125 0, /* __u8 Unicode */
126 't', /* __u8 Unicode */
127 0, /* __u8 Unicode */
128 ' ', /* __u8 Unicode */
129 0, /* __u8 Unicode */
130 'H', /* __u8 Unicode */
131 0, /* __u8 Unicode */
132 'u', /* __u8 Unicode */
133 0, /* __u8 Unicode */
134 'b', /* __u8 Unicode */
135 0, /* __u8 Unicode */
140 * This function writes the data toggle value.
142 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
144 u16 toggle = usb_gettoggle(dev, ep, dir_out);
148 csr = readw(&musbr->txcsr);
150 if (csr & MUSB_TXCSR_MODE)
151 csr = MUSB_TXCSR_CLRDATATOG;
154 writew(csr, &musbr->txcsr);
156 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
157 writew(csr, &musbr->txcsr);
158 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
159 writew(csr, &musbr->txcsr);
163 csr = readw(&musbr->txcsr);
164 if (csr & MUSB_TXCSR_MODE)
165 csr = MUSB_RXCSR_CLRDATATOG;
168 writew(csr, &musbr->rxcsr);
170 csr = readw(&musbr->rxcsr);
171 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
172 writew(csr, &musbr->rxcsr);
173 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
174 writew(csr, &musbr->rxcsr);
180 * This function checks if RxStall has occured on the endpoint. If a RxStall
181 * has occured, the RxStall is cleared and 1 is returned. If RxStall has
182 * not occured, 0 is returned.
184 static u8 check_stall(u8 ep, u8 dir_out)
190 csr = readw(&musbr->txcsr);
191 if (csr & MUSB_CSR0_H_RXSTALL) {
192 csr &= ~MUSB_CSR0_H_RXSTALL;
193 writew(csr, &musbr->txcsr);
196 } else { /* For non-ep0 */
197 if (dir_out) { /* is it tx ep */
198 csr = readw(&musbr->txcsr);
199 if (csr & MUSB_TXCSR_H_RXSTALL) {
200 csr &= ~MUSB_TXCSR_H_RXSTALL;
201 writew(csr, &musbr->txcsr);
204 } else { /* is it rx ep */
205 csr = readw(&musbr->rxcsr);
206 if (csr & MUSB_RXCSR_H_RXSTALL) {
207 csr &= ~MUSB_RXCSR_H_RXSTALL;
208 writew(csr, &musbr->rxcsr);
217 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
218 * error and -2 for stall.
220 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
224 int timeout = CONFIG_MUSB_TIMEOUT;
227 csr = readw(&musbr->txcsr);
228 if (csr & MUSB_CSR0_H_ERROR) {
229 csr &= ~MUSB_CSR0_H_ERROR;
230 writew(csr, &musbr->txcsr);
231 dev->status = USB_ST_CRC_ERR;
237 case MUSB_CSR0_TXPKTRDY:
238 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
239 if (check_stall(MUSB_CONTROL_EP, 0)) {
240 dev->status = USB_ST_STALLED;
247 case MUSB_CSR0_RXPKTRDY:
248 if (check_stall(MUSB_CONTROL_EP, 0)) {
249 dev->status = USB_ST_STALLED;
252 if (csr & MUSB_CSR0_RXPKTRDY)
256 case MUSB_CSR0_H_REQPKT:
257 if (!(csr & MUSB_CSR0_H_REQPKT)) {
258 if (check_stall(MUSB_CONTROL_EP, 0)) {
259 dev->status = USB_ST_STALLED;
267 /* Check the timeout */
271 dev->status = USB_ST_CRC_ERR;
281 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
283 static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
286 int timeout = CONFIG_MUSB_TIMEOUT;
289 if (check_stall(ep, 1)) {
290 dev->status = USB_ST_STALLED;
294 csr = readw(&musbr->txcsr);
295 if (csr & MUSB_TXCSR_H_ERROR) {
296 dev->status = USB_ST_CRC_ERR;
300 /* Check the timeout */
304 dev->status = USB_ST_CRC_ERR;
308 } while (csr & MUSB_TXCSR_TXPKTRDY);
313 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
315 static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
318 int timeout = CONFIG_MUSB_TIMEOUT;
321 if (check_stall(ep, 0)) {
322 dev->status = USB_ST_STALLED;
326 csr = readw(&musbr->rxcsr);
327 if (csr & MUSB_RXCSR_H_ERROR) {
328 dev->status = USB_ST_CRC_ERR;
332 /* Check the timeout */
336 dev->status = USB_ST_CRC_ERR;
340 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
345 * This function performs the setup phase of the control transfer
347 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
352 /* write the control request to ep0 fifo */
353 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
355 /* enable transfer of setup packet */
356 csr = readw(&musbr->txcsr);
357 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
358 writew(csr, &musbr->txcsr);
360 /* wait until the setup packet is transmitted */
361 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
367 * This function handles the control transfer in data phase
369 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
374 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
375 u8 *rxbuff = (u8 *)buffer;
379 while (rxlen < len) {
380 /* Determine the next read length */
381 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
383 /* Set the ReqPkt bit */
384 csr = readw(&musbr->txcsr);
385 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
386 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
390 /* Actual number of bytes received by usb */
391 rxedlength = readb(&musbr->rxcount);
393 /* Read the data from the RxFIFO */
394 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
396 /* Clear the RxPktRdy Bit */
397 csr = readw(&musbr->txcsr);
398 csr &= ~MUSB_CSR0_RXPKTRDY;
399 writew(csr, &musbr->txcsr);
402 if (rxedlength != nextlen) {
403 dev->act_len += rxedlength;
407 dev->act_len = rxlen;
413 * This function handles the control transfer out data phase
415 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
420 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
421 u8 *txbuff = (u8 *)buffer;
424 while (txlen < len) {
425 /* Determine the next write length */
426 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
428 /* Load the data to send in FIFO */
429 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
431 /* Set TXPKTRDY bit */
432 csr = readw(&musbr->txcsr);
433 writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY,
435 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
440 dev->act_len = txlen;
446 * This function handles the control transfer out status phase
448 static int ctrlreq_out_status_phase(struct usb_device *dev)
453 /* Set the StatusPkt bit */
454 csr = readw(&musbr->txcsr);
455 csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY |
456 MUSB_CSR0_H_STATUSPKT);
457 writew(csr, &musbr->txcsr);
459 /* Wait until TXPKTRDY bit is cleared */
460 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
465 * This function handles the control transfer in status phase
467 static int ctrlreq_in_status_phase(struct usb_device *dev)
472 /* Set the StatusPkt bit and ReqPkt bit */
473 csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
474 writew(csr, &musbr->txcsr);
475 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
477 /* clear StatusPkt bit and RxPktRdy bit */
478 csr = readw(&musbr->txcsr);
479 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
480 writew(csr, &musbr->txcsr);
485 * determines the speed of the device (High/Full/Slow)
487 static u8 get_dev_speed(struct usb_device *dev)
489 return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
490 ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
491 MUSB_TYPE_SPEED_FULL);
495 * configure the hub address and the port address.
497 static void config_hub_port(struct usb_device *dev, u8 ep)
502 /* Find out the nearest parent which is high speed */
503 while (dev->parent->parent != NULL)
504 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
509 /* determine the port address at that hub */
510 hub = dev->parent->devnum;
511 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
512 if (dev->parent->children[chid] == dev)
515 #ifndef MUSB_NO_MULTIPOINT
516 /* configure the hub address and the port address */
517 writeb(hub, &musbr->tar[ep].txhubaddr);
518 writeb((chid + 1), &musbr->tar[ep].txhubport);
519 writeb(hub, &musbr->tar[ep].rxhubaddr);
520 writeb((chid + 1), &musbr->tar[ep].rxhubport);
524 #ifdef MUSB_NO_MULTIPOINT
526 static void musb_port_reset(int do_reset)
528 u8 power = readb(&musbr->power);
532 writeb(power | MUSB_POWER_RESET, &musbr->power);
533 port_status |= USB_PORT_STAT_RESET;
534 port_status &= ~USB_PORT_STAT_ENABLE;
537 writeb(power & ~MUSB_POWER_RESET, &musbr->power);
539 power = readb(&musbr->power);
540 if (power & MUSB_POWER_HSMODE)
541 port_status |= USB_PORT_STAT_HIGH_SPEED;
543 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
544 port_status |= USB_PORT_STAT_ENABLE
545 | (USB_PORT_STAT_C_RESET << 16)
546 | (USB_PORT_STAT_C_ENABLE << 16);
553 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
554 void *buffer, int transfer_len,
555 struct devrequest *cmd)
557 int leni = transfer_len;
561 const u8 *data_buf = (u8 *) datab;
568 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
569 debug("Root-Hub submit IRQ: NOT implemented\n");
573 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
574 wValue = swap_16(cmd->value);
575 wIndex = swap_16(cmd->index);
576 wLength = swap_16(cmd->length);
578 debug("--- HUB ----------------------------------------\n");
579 debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
580 bmRType_bReq, wValue, wIndex, wLength);
581 debug("------------------------------------------------\n");
583 switch (bmRType_bReq) {
585 debug("RH_GET_STATUS\n");
587 *(__u16 *) data_buf = swap_16(1);
591 case RH_GET_STATUS | RH_INTERFACE:
592 debug("RH_GET_STATUS | RH_INTERFACE\n");
594 *(__u16 *) data_buf = swap_16(0);
598 case RH_GET_STATUS | RH_ENDPOINT:
599 debug("RH_GET_STATUS | RH_ENDPOINT\n");
601 *(__u16 *) data_buf = swap_16(0);
605 case RH_GET_STATUS | RH_CLASS:
606 debug("RH_GET_STATUS | RH_CLASS\n");
608 *(__u32 *) data_buf = swap_32(0);
612 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
613 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
615 int_usb = readw(&musbr->intrusb);
616 if (int_usb & MUSB_INTR_CONNECT) {
617 port_status |= USB_PORT_STAT_CONNECTION
618 | (USB_PORT_STAT_C_CONNECTION << 16);
619 port_status |= USB_PORT_STAT_HIGH_SPEED
620 | USB_PORT_STAT_ENABLE;
623 if (port_status & USB_PORT_STAT_RESET)
626 *(__u32 *) data_buf = swap_32(port_status);
630 case RH_CLEAR_FEATURE | RH_ENDPOINT:
631 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
634 case RH_ENDPOINT_STALL:
635 debug("C_HUB_ENDPOINT_STALL\n");
639 port_status &= ~(1 << wValue);
642 case RH_CLEAR_FEATURE | RH_CLASS:
643 debug("RH_CLEAR_FEATURE | RH_CLASS\n");
646 case RH_C_HUB_LOCAL_POWER:
647 debug("C_HUB_LOCAL_POWER\n");
651 case RH_C_HUB_OVER_CURRENT:
652 debug("C_HUB_OVER_CURRENT\n");
656 port_status &= ~(1 << wValue);
659 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
660 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
667 case RH_PORT_SUSPEND:
675 case RH_C_PORT_CONNECTION:
679 case RH_C_PORT_ENABLE:
683 case RH_C_PORT_SUSPEND:
687 case RH_C_PORT_OVER_CURRENT:
691 case RH_C_PORT_RESET:
696 debug("invalid wValue\n");
697 stat = USB_ST_STALLED;
700 port_status &= ~(1 << wValue);
703 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
704 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
707 case RH_PORT_SUSPEND:
725 debug("invalid wValue\n");
726 stat = USB_ST_STALLED;
729 port_status |= 1 << wValue;
733 debug("RH_SET_ADDRESS\n");
739 case RH_GET_DESCRIPTOR:
740 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
743 case (USB_DT_DEVICE << 8): /* device descriptor */
744 len = min_t(unsigned int,
745 leni, min_t(unsigned int,
746 sizeof(root_hub_dev_des),
748 data_buf = root_hub_dev_des;
751 case (USB_DT_CONFIG << 8): /* configuration descriptor */
752 len = min_t(unsigned int,
753 leni, min_t(unsigned int,
754 sizeof(root_hub_config_des),
756 data_buf = root_hub_config_des;
759 case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
760 len = min_t(unsigned int,
761 leni, min_t(unsigned int,
762 sizeof(root_hub_str_index0),
764 data_buf = root_hub_str_index0;
767 case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
768 len = min_t(unsigned int,
769 leni, min_t(unsigned int,
770 sizeof(root_hub_str_index1),
772 data_buf = root_hub_str_index1;
776 debug("invalid wValue\n");
777 stat = USB_ST_STALLED;
782 case RH_GET_DESCRIPTOR | RH_CLASS: {
783 u8 *_data_buf = (u8 *) datab;
784 debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
786 _data_buf[0] = 0x09; /* min length; */
788 _data_buf[2] = 0x1; /* 1 port */
789 _data_buf[3] = 0x01; /* per-port power switching */
790 _data_buf[3] |= 0x10; /* no overcurrent reporting */
792 /* Corresponds to data_buf[4-7] */
799 len = min_t(unsigned int, leni,
800 min_t(unsigned int, data_buf[0], wLength));
804 case RH_GET_CONFIGURATION:
805 debug("RH_GET_CONFIGURATION\n");
807 *(__u8 *) data_buf = 0x01;
811 case RH_SET_CONFIGURATION:
812 debug("RH_SET_CONFIGURATION\n");
818 debug("*** *** *** unsupported root hub command *** *** ***\n");
819 stat = USB_ST_STALLED;
822 len = min_t(int, len, leni);
823 if (buffer != data_buf)
824 memcpy(buffer, data_buf, len);
828 debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
833 static void musb_rh_init(void)
841 static void musb_rh_init(void) {}
846 * do a control transfer
848 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
849 int len, struct devrequest *setup)
851 int devnum = usb_pipedevice(pipe);
854 #ifdef MUSB_NO_MULTIPOINT
855 /* Control message is for the HUB? */
856 if (devnum == rh_devnum) {
857 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
863 /* select control endpoint */
864 writeb(MUSB_CONTROL_EP, &musbr->index);
865 readw(&musbr->txcsr);
867 #ifndef MUSB_NO_MULTIPOINT
868 /* target addr and (for multipoint) hub addr/port */
869 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
870 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
873 /* configure the hub address and the port number as required */
874 devspeed = get_dev_speed(dev);
875 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
876 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
877 config_hub_port(dev, MUSB_CONTROL_EP);
878 writeb(devspeed << 6, &musbr->txtype);
880 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
881 #ifndef MUSB_NO_MULTIPOINT
882 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
883 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
884 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
885 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
889 /* Control transfer setup phase */
890 if (ctrlreq_setup_phase(dev, setup) < 0)
893 switch (setup->request) {
894 case USB_REQ_GET_DESCRIPTOR:
895 case USB_REQ_GET_CONFIGURATION:
896 case USB_REQ_GET_INTERFACE:
897 case USB_REQ_GET_STATUS:
898 case USB_MSC_BBB_GET_MAX_LUN:
899 /* control transfer in-data-phase */
900 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
902 /* control transfer out-status-phase */
903 if (ctrlreq_out_status_phase(dev) < 0)
907 case USB_REQ_SET_ADDRESS:
908 case USB_REQ_SET_CONFIGURATION:
909 case USB_REQ_SET_FEATURE:
910 case USB_REQ_SET_INTERFACE:
911 case USB_REQ_CLEAR_FEATURE:
912 case USB_MSC_BBB_RESET:
913 /* control transfer in status phase */
914 if (ctrlreq_in_status_phase(dev) < 0)
918 case USB_REQ_SET_DESCRIPTOR:
919 /* control transfer out data phase */
920 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
922 /* control transfer in status phase */
923 if (ctrlreq_in_status_phase(dev) < 0)
928 /* unhandled control transfer */
935 #ifdef MUSB_NO_MULTIPOINT
936 /* Set device address to USB_FADDR register */
937 if (setup->request == USB_REQ_SET_ADDRESS)
938 writeb(dev->devnum, &musbr->faddr);
947 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
948 void *buffer, int len)
950 int dir_out = usb_pipeout(pipe);
951 int ep = usb_pipeendpoint(pipe);
952 #ifndef MUSB_NO_MULTIPOINT
953 int devnum = usb_pipedevice(pipe);
961 /* select bulk endpoint */
962 writeb(MUSB_BULK_EP, &musbr->index);
964 #ifndef MUSB_NO_MULTIPOINT
965 /* write the address of the device */
967 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
969 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
972 /* configure the hub address and the port number as required */
973 devspeed = get_dev_speed(dev);
974 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
975 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
977 * MUSB is in high speed and the destination device is full
978 * speed device. So configure the hub address and port
981 config_hub_port(dev, MUSB_BULK_EP);
983 #ifndef MUSB_NO_MULTIPOINT
985 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
986 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
988 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
989 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
992 devspeed = musb_cfg.musb_speed;
995 /* Write the saved toggle bit value */
996 write_toggle(dev, ep, dir_out);
998 if (dir_out) { /* bulk-out transfer */
999 /* Program the TxType register */
1000 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1001 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
1002 (ep & MUSB_TYPE_REMOTE_END);
1003 writeb(type, &musbr->txtype);
1005 /* Write maximum packet size to the TxMaxp register */
1006 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
1007 while (txlen < len) {
1008 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
1009 (len-txlen) : dev->epmaxpacketout[ep];
1011 #ifdef CONFIG_USB_BLACKFIN
1012 /* Set the transfer data size */
1013 writew(nextlen, &musbr->txcount);
1016 /* Write the data to the FIFO */
1017 write_fifo(MUSB_BULK_EP, nextlen,
1018 (void *)(((u8 *)buffer) + txlen));
1020 /* Set the TxPktRdy bit */
1021 csr = readw(&musbr->txcsr);
1022 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
1024 /* Wait until the TxPktRdy bit is cleared */
1025 if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
1026 readw(&musbr->txcsr);
1027 usb_settoggle(dev, ep, dir_out,
1028 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
1029 dev->act_len = txlen;
1035 /* Keep a copy of the data toggle bit */
1036 csr = readw(&musbr->txcsr);
1037 usb_settoggle(dev, ep, dir_out,
1038 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
1039 } else { /* bulk-in transfer */
1040 /* Write the saved toggle bit value */
1041 write_toggle(dev, ep, dir_out);
1043 /* Program the RxType register */
1044 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1045 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
1046 (ep & MUSB_TYPE_REMOTE_END);
1047 writeb(type, &musbr->rxtype);
1049 /* Write the maximum packet size to the RxMaxp register */
1050 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1051 while (txlen < len) {
1052 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1053 (len-txlen) : dev->epmaxpacketin[ep];
1055 /* Set the ReqPkt bit */
1056 csr = readw(&musbr->rxcsr);
1057 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1059 /* Wait until the RxPktRdy bit is set */
1060 if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
1061 csr = readw(&musbr->rxcsr);
1062 usb_settoggle(dev, ep, dir_out,
1063 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1064 csr &= ~MUSB_RXCSR_RXPKTRDY;
1065 writew(csr, &musbr->rxcsr);
1066 dev->act_len = txlen;
1070 /* Read the data from the FIFO */
1071 read_fifo(MUSB_BULK_EP, nextlen,
1072 (void *)(((u8 *)buffer) + txlen));
1074 /* Clear the RxPktRdy bit */
1075 csr = readw(&musbr->rxcsr);
1076 csr &= ~MUSB_RXCSR_RXPKTRDY;
1077 writew(csr, &musbr->rxcsr);
1081 /* Keep a copy of the data toggle bit */
1082 csr = readw(&musbr->rxcsr);
1083 usb_settoggle(dev, ep, dir_out,
1084 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1087 /* bulk transfer is complete */
1094 * This function initializes the usb controller module.
1096 int usb_lowlevel_init(int index, void **controller)
1103 if (musb_platform_init() == -1)
1106 /* Configure all the endpoint FIFO's and start usb controller */
1107 musbr = musb_cfg.regs;
1108 musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1112 * Wait until musb is enabled in host mode with a timeout. There
1113 * should be a usb device connected.
1115 timeout = musb_cfg.timeout;
1117 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1120 /* if musb core is not in host mode, then return */
1124 /* start usb bus reset */
1125 power = readb(&musbr->power);
1126 writeb(power | MUSB_POWER_RESET, &musbr->power);
1128 /* After initiating a usb reset, wait for about 20ms to 30ms */
1131 /* stop usb bus reset */
1132 power = readb(&musbr->power);
1133 power &= ~MUSB_POWER_RESET;
1134 writeb(power, &musbr->power);
1136 /* Determine if the connected device is a high/full/low speed device */
1137 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1138 MUSB_TYPE_SPEED_HIGH :
1139 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1140 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1145 * This function stops the operation of the davinci usb module.
1147 int usb_lowlevel_stop(int index)
1149 /* Reset the USB module */
1150 musb_platform_deinit();
1151 writeb(0, &musbr->devctl);
1156 * This function supports usb interrupt transfers. Currently, usb interrupt
1157 * transfers are not supported.
1159 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1160 void *buffer, int len, int interval)
1162 int dir_out = usb_pipeout(pipe);
1163 int ep = usb_pipeendpoint(pipe);
1164 #ifndef MUSB_NO_MULTIPOINT
1165 int devnum = usb_pipedevice(pipe);
1173 /* select interrupt endpoint */
1174 writeb(MUSB_INTR_EP, &musbr->index);
1176 #ifndef MUSB_NO_MULTIPOINT
1177 /* write the address of the device */
1179 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1181 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1184 /* configure the hub address and the port number as required */
1185 devspeed = get_dev_speed(dev);
1186 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1187 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
1189 * MUSB is in high speed and the destination device is full
1190 * speed device. So configure the hub address and port
1191 * address registers.
1193 config_hub_port(dev, MUSB_INTR_EP);
1195 #ifndef MUSB_NO_MULTIPOINT
1197 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1198 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1200 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1201 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1204 devspeed = musb_cfg.musb_speed;
1207 /* Write the saved toggle bit value */
1208 write_toggle(dev, ep, dir_out);
1210 if (!dir_out) { /* intrrupt-in transfer */
1211 /* Write the saved toggle bit value */
1212 write_toggle(dev, ep, dir_out);
1213 writeb(interval, &musbr->rxinterval);
1215 /* Program the RxType register */
1216 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1217 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1218 (ep & MUSB_TYPE_REMOTE_END);
1219 writeb(type, &musbr->rxtype);
1221 /* Write the maximum packet size to the RxMaxp register */
1222 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1224 while (txlen < len) {
1225 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1226 (len-txlen) : dev->epmaxpacketin[ep];
1228 /* Set the ReqPkt bit */
1229 csr = readw(&musbr->rxcsr);
1230 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1232 /* Wait until the RxPktRdy bit is set */
1233 if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
1234 csr = readw(&musbr->rxcsr);
1235 usb_settoggle(dev, ep, dir_out,
1236 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1237 csr &= ~MUSB_RXCSR_RXPKTRDY;
1238 writew(csr, &musbr->rxcsr);
1239 dev->act_len = txlen;
1243 /* Read the data from the FIFO */
1244 read_fifo(MUSB_INTR_EP, nextlen,
1245 (void *)(((u8 *)buffer) + txlen));
1247 /* Clear the RxPktRdy bit */
1248 csr = readw(&musbr->rxcsr);
1249 csr &= ~MUSB_RXCSR_RXPKTRDY;
1250 writew(csr, &musbr->rxcsr);
1254 /* Keep a copy of the data toggle bit */
1255 csr = readw(&musbr->rxcsr);
1256 usb_settoggle(dev, ep, dir_out,
1257 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1260 /* interrupt transfer is complete */
1261 dev->irq_status = 0;
1262 dev->irq_act_len = len;
1263 dev->irq_handle(dev);