2 * MUSB OTG peripheral driver ep0 handling
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <linux/kernel.h>
38 #include <linux/list.h>
39 #include <linux/timer.h>
40 #include <linux/spinlock.h>
41 #include <linux/device.h>
42 #include <linux/interrupt.h>
45 #include "linux-compat.h"
48 #include "musb_core.h"
50 /* ep0 is always musb->endpoints[0].ep_in */
51 #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
54 * locking note: we use only the controller lock, for simpler correctness.
55 * It's always held with IRQs blocked.
57 * It protects the ep0 request queue as well as ep0_state, not just the
58 * controller and indexed registers. And that lock stays held unless it
59 * needs to be dropped to allow reentering this driver ... like upcalls to
60 * the gadget driver, or adjusting endpoint halt status.
63 static char *decode_ep0stage(u8 stage)
66 case MUSB_EP0_STAGE_IDLE: return "idle";
67 case MUSB_EP0_STAGE_SETUP: return "setup";
68 case MUSB_EP0_STAGE_TX: return "in";
69 case MUSB_EP0_STAGE_RX: return "out";
70 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
71 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
72 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
77 /* handle a standard GET_STATUS request
78 * Context: caller holds controller lock
80 static int service_tx_status_request(
82 const struct usb_ctrlrequest *ctrlrequest)
84 void __iomem *mbase = musb->mregs;
86 u8 result[2], epnum = 0;
87 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
92 case USB_RECIP_DEVICE:
93 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
94 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
96 result[0] |= musb->g.b_hnp_enable
97 << USB_DEVICE_B_HNP_ENABLE;
98 result[0] |= musb->g.a_alt_hnp_support
99 << USB_DEVICE_A_ALT_HNP_SUPPORT;
100 result[0] |= musb->g.a_hnp_support
101 << USB_DEVICE_A_HNP_SUPPORT;
105 case USB_RECIP_INTERFACE:
109 case USB_RECIP_ENDPOINT: {
115 epnum = (u8) ctrlrequest->wIndex;
121 is_in = epnum & USB_DIR_IN;
124 ep = &musb->endpoints[epnum].ep_in;
126 ep = &musb->endpoints[epnum].ep_out;
128 regs = musb->endpoints[epnum].regs;
130 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
135 musb_ep_select(mbase, epnum);
137 tmp = musb_readw(regs, MUSB_TXCSR)
138 & MUSB_TXCSR_P_SENDSTALL;
140 tmp = musb_readw(regs, MUSB_RXCSR)
141 & MUSB_RXCSR_P_SENDSTALL;
142 musb_ep_select(mbase, 0);
144 result[0] = tmp ? 1 : 0;
148 /* class, vendor, etc ... delegate */
153 /* fill up the fifo; caller updates csr0 */
155 u16 len = le16_to_cpu(ctrlrequest->wLength);
159 musb_write_fifo(&musb->endpoints[0], len, result);
166 * handle a control-IN request, the end0 buffer contains the current request
167 * that is supposed to be a standard control request. Assumes the fifo to
168 * be at least 2 bytes long.
170 * @return 0 if the request was NOT HANDLED,
172 * > 0 when the request is processed
174 * Context: caller holds controller lock
177 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
179 int handled = 0; /* not handled */
181 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
182 == USB_TYPE_STANDARD) {
183 switch (ctrlrequest->bRequest) {
184 case USB_REQ_GET_STATUS:
185 handled = service_tx_status_request(musb,
189 /* case USB_REQ_SYNC_FRAME: */
199 * Context: caller holds controller lock
201 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
203 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
207 * Tries to start B-device HNP negotiation if enabled via sysfs
209 static inline void musb_try_b_hnp_enable(struct musb *musb)
211 void __iomem *mbase = musb->mregs;
214 dev_dbg(musb->controller, "HNP: Setting HR\n");
215 devctl = musb_readb(mbase, MUSB_DEVCTL);
216 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
220 * Handle all control requests with no DATA stage, including standard
222 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
223 * always delegated to the gadget driver
224 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
225 * always handled here, except for class/vendor/... features
227 * Context: caller holds controller lock
230 service_zero_data_request(struct musb *musb,
231 struct usb_ctrlrequest *ctrlrequest)
232 __releases(musb->lock)
233 __acquires(musb->lock)
235 int handled = -EINVAL;
236 void __iomem *mbase = musb->mregs;
237 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
239 /* the gadget driver handles everything except what we MUST handle */
240 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
241 == USB_TYPE_STANDARD) {
242 switch (ctrlrequest->bRequest) {
243 case USB_REQ_SET_ADDRESS:
244 /* change it after the status stage */
245 musb->set_address = true;
246 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
250 case USB_REQ_CLEAR_FEATURE:
252 case USB_RECIP_DEVICE:
253 if (ctrlrequest->wValue
254 != USB_DEVICE_REMOTE_WAKEUP)
256 musb->may_wakeup = 0;
259 case USB_RECIP_INTERFACE:
261 case USB_RECIP_ENDPOINT:{
263 ctrlrequest->wIndex & 0x0f;
264 struct musb_ep *musb_ep;
265 struct musb_hw_ep *ep;
266 struct musb_request *request;
271 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
272 ctrlrequest->wValue != USB_ENDPOINT_HALT)
275 ep = musb->endpoints + epnum;
277 is_in = ctrlrequest->wIndex & USB_DIR_IN;
279 musb_ep = &ep->ep_in;
281 musb_ep = &ep->ep_out;
286 /* Ignore request if endpoint is wedged */
290 musb_ep_select(mbase, epnum);
292 csr = musb_readw(regs, MUSB_TXCSR);
293 csr |= MUSB_TXCSR_CLRDATATOG |
294 MUSB_TXCSR_P_WZC_BITS;
295 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
296 MUSB_TXCSR_P_SENTSTALL |
297 MUSB_TXCSR_TXPKTRDY);
298 musb_writew(regs, MUSB_TXCSR, csr);
300 csr = musb_readw(regs, MUSB_RXCSR);
301 csr |= MUSB_RXCSR_CLRDATATOG |
302 MUSB_RXCSR_P_WZC_BITS;
303 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
304 MUSB_RXCSR_P_SENTSTALL);
305 musb_writew(regs, MUSB_RXCSR, csr);
308 /* Maybe start the first request in the queue */
309 request = next_request(musb_ep);
310 if (!musb_ep->busy && request) {
311 dev_dbg(musb->controller, "restarting the request\n");
312 musb_ep_restart(musb, request);
315 /* select ep0 again */
316 musb_ep_select(mbase, 0);
319 /* class, vendor, etc ... delegate */
325 case USB_REQ_SET_FEATURE:
327 case USB_RECIP_DEVICE:
329 switch (ctrlrequest->wValue) {
330 case USB_DEVICE_REMOTE_WAKEUP:
331 musb->may_wakeup = 1;
333 case USB_DEVICE_TEST_MODE:
334 if (musb->g.speed != USB_SPEED_HIGH)
336 if (ctrlrequest->wIndex & 0xff)
339 switch (ctrlrequest->wIndex >> 8) {
341 pr_debug("TEST_J\n");
348 pr_debug("TEST_K\n");
354 pr_debug("TEST_SE0_NAK\n");
360 pr_debug("TEST_PACKET\n");
367 pr_debug("TEST_FORCE_HS\n");
373 pr_debug("TEST_FORCE_FS\n");
378 /* TEST_FIFO_ACCESS */
379 pr_debug("TEST_FIFO_ACCESS\n");
381 MUSB_TEST_FIFO_ACCESS;
384 /* TEST_FORCE_HOST */
385 pr_debug("TEST_FORCE_HOST\n");
387 MUSB_TEST_FORCE_HOST;
393 /* enter test mode after irq */
395 musb->test_mode = true;
397 case USB_DEVICE_B_HNP_ENABLE:
400 musb->g.b_hnp_enable = 1;
401 musb_try_b_hnp_enable(musb);
403 case USB_DEVICE_A_HNP_SUPPORT:
406 musb->g.a_hnp_support = 1;
408 case USB_DEVICE_A_ALT_HNP_SUPPORT:
411 musb->g.a_alt_hnp_support = 1;
413 case USB_DEVICE_DEBUG_MODE:
423 case USB_RECIP_INTERFACE:
426 case USB_RECIP_ENDPOINT:{
428 ctrlrequest->wIndex & 0x0f;
429 struct musb_ep *musb_ep;
430 struct musb_hw_ep *ep;
435 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
436 ctrlrequest->wValue != USB_ENDPOINT_HALT)
439 ep = musb->endpoints + epnum;
441 is_in = ctrlrequest->wIndex & USB_DIR_IN;
443 musb_ep = &ep->ep_in;
445 musb_ep = &ep->ep_out;
449 musb_ep_select(mbase, epnum);
451 csr = musb_readw(regs, MUSB_TXCSR);
452 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
453 csr |= MUSB_TXCSR_FLUSHFIFO;
454 csr |= MUSB_TXCSR_P_SENDSTALL
455 | MUSB_TXCSR_CLRDATATOG
456 | MUSB_TXCSR_P_WZC_BITS;
457 musb_writew(regs, MUSB_TXCSR, csr);
459 csr = musb_readw(regs, MUSB_RXCSR);
460 csr |= MUSB_RXCSR_P_SENDSTALL
461 | MUSB_RXCSR_FLUSHFIFO
462 | MUSB_RXCSR_CLRDATATOG
463 | MUSB_RXCSR_P_WZC_BITS;
464 musb_writew(regs, MUSB_RXCSR, csr);
467 /* select ep0 again */
468 musb_ep_select(mbase, 0);
473 /* class, vendor, etc ... delegate */
479 /* delegate SET_CONFIGURATION, etc */
487 /* we have an ep0out data packet
488 * Context: caller holds controller lock
490 static void ep0_rxstate(struct musb *musb)
492 void __iomem *regs = musb->control_ep->regs;
493 struct musb_request *request;
494 struct usb_request *req;
497 request = next_ep0_request(musb);
498 req = &request->request;
500 /* read packet and ack; or stall because of gadget driver bug:
501 * should have provided the rx buffer before setup() returned.
504 void *buf = req->buf + req->actual;
505 unsigned len = req->length - req->actual;
507 /* read the buffer */
508 count = musb_readb(regs, MUSB_COUNT0);
510 req->status = -EOVERFLOW;
513 musb_read_fifo(&musb->endpoints[0], count, buf);
514 req->actual += count;
515 csr = MUSB_CSR0_P_SVDRXPKTRDY;
516 if (count < 64 || req->actual == req->length) {
517 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
518 csr |= MUSB_CSR0_P_DATAEND;
522 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
525 /* Completion handler may choose to stall, e.g. because the
526 * message just received holds invalid data.
530 musb_g_ep0_giveback(musb, req);
535 musb_ep_select(musb->mregs, 0);
536 musb_writew(regs, MUSB_CSR0, csr);
540 * transmitting to the host (IN), this code might be called from IRQ
541 * and from kernel thread.
543 * Context: caller holds controller lock
545 static void ep0_txstate(struct musb *musb)
547 void __iomem *regs = musb->control_ep->regs;
548 struct musb_request *req = next_ep0_request(musb);
549 struct usb_request *request;
550 u16 csr = MUSB_CSR0_TXPKTRDY;
556 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
560 request = &req->request;
563 fifo_src = (u8 *) request->buf + request->actual;
564 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
565 request->length - request->actual);
566 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
567 request->actual += fifo_count;
569 /* update the flags */
570 if (fifo_count < MUSB_MAX_END0_PACKET
571 || (request->actual == request->length
572 && !request->zero)) {
573 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
574 csr |= MUSB_CSR0_P_DATAEND;
578 /* send it out, triggering a "txpktrdy cleared" irq */
579 musb_ep_select(musb->mregs, 0);
580 musb_writew(regs, MUSB_CSR0, csr);
582 /* report completions as soon as the fifo's loaded; there's no
583 * win in waiting till this last packet gets acked. (other than
584 * very precise fault reporting, needed by USB TMC; possible with
585 * this hardware, but not usable from portable gadget drivers.)
589 musb_g_ep0_giveback(musb, request);
597 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
598 * Fields are left in USB byte-order.
600 * Context: caller holds controller lock.
603 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
605 struct musb_request *r;
606 void __iomem *regs = musb->control_ep->regs;
608 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
610 /* NOTE: earlier 2.6 versions changed setup packets to host
611 * order, but now USB packets always stay in USB byte order.
613 dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
616 le16_to_cpu(req->wValue),
617 le16_to_cpu(req->wIndex),
618 le16_to_cpu(req->wLength));
620 /* clean up any leftover transfers */
621 r = next_ep0_request(musb);
623 musb_g_ep0_giveback(musb, &r->request);
625 /* For zero-data requests we want to delay the STATUS stage to
626 * avoid SETUPEND errors. If we read data (OUT), delay accepting
627 * packets until there's a buffer to store them in.
629 * If we write data, the controller acts happier if we enable
630 * the TX FIFO right away, and give the controller a moment
633 musb->set_address = false;
634 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
635 if (req->wLength == 0) {
636 if (req->bRequestType & USB_DIR_IN)
637 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
638 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
639 } else if (req->bRequestType & USB_DIR_IN) {
640 musb->ep0_state = MUSB_EP0_STAGE_TX;
641 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
642 while ((musb_readw(regs, MUSB_CSR0)
643 & MUSB_CSR0_RXPKTRDY) != 0)
647 musb->ep0_state = MUSB_EP0_STAGE_RX;
651 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
652 __releases(musb->lock)
653 __acquires(musb->lock)
656 if (!musb->gadget_driver)
658 spin_unlock(&musb->lock);
659 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
660 spin_lock(&musb->lock);
665 * Handle peripheral ep0 interrupt
667 * Context: irq handler; we won't re-enter the driver that way.
669 irqreturn_t musb_g_ep0_irq(struct musb *musb)
673 void __iomem *mbase = musb->mregs;
674 void __iomem *regs = musb->endpoints[0].regs;
675 irqreturn_t retval = IRQ_NONE;
677 musb_ep_select(mbase, 0); /* select ep0 */
678 csr = musb_readw(regs, MUSB_CSR0);
679 len = musb_readb(regs, MUSB_COUNT0);
681 dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
683 musb_readb(mbase, MUSB_FADDR),
684 decode_ep0stage(musb->ep0_state));
686 if (csr & MUSB_CSR0_P_DATAEND) {
688 * If DATAEND is set we should not call the callback,
689 * hence the status stage is not complete.
694 /* I sent a stall.. need to acknowledge it now.. */
695 if (csr & MUSB_CSR0_P_SENTSTALL) {
696 musb_writew(regs, MUSB_CSR0,
697 csr & ~MUSB_CSR0_P_SENTSTALL);
698 retval = IRQ_HANDLED;
699 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
700 csr = musb_readw(regs, MUSB_CSR0);
703 /* request ended "early" */
704 if (csr & MUSB_CSR0_P_SETUPEND) {
705 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
706 retval = IRQ_HANDLED;
707 /* Transition into the early status phase */
708 switch (musb->ep0_state) {
709 case MUSB_EP0_STAGE_TX:
710 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
712 case MUSB_EP0_STAGE_RX:
713 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
716 ERR("SetupEnd came in a wrong ep0stage %s\n",
717 decode_ep0stage(musb->ep0_state));
719 csr = musb_readw(regs, MUSB_CSR0);
720 /* NOTE: request may need completion */
723 /* docs from Mentor only describe tx, rx, and idle/setup states.
724 * we need to handle nuances around status stages, and also the
725 * case where status and setup stages come back-to-back ...
727 switch (musb->ep0_state) {
729 case MUSB_EP0_STAGE_TX:
730 /* irq on clearing txpktrdy */
731 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
733 retval = IRQ_HANDLED;
737 case MUSB_EP0_STAGE_RX:
738 /* irq on set rxpktrdy */
739 if (csr & MUSB_CSR0_RXPKTRDY) {
741 retval = IRQ_HANDLED;
745 case MUSB_EP0_STAGE_STATUSIN:
746 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
748 /* update address (if needed) only @ the end of the
749 * status phase per usb spec, which also guarantees
750 * we get 10 msec to receive this irq... until this
751 * is done we won't see the next packet.
753 if (musb->set_address) {
754 musb->set_address = false;
755 musb_writeb(mbase, MUSB_FADDR, musb->address);
758 /* enter test mode if needed (exit by reset) */
759 else if (musb->test_mode) {
760 dev_dbg(musb->controller, "entering TESTMODE\n");
762 if (MUSB_TEST_PACKET == musb->test_mode_nr)
763 musb_load_testpacket(musb);
765 musb_writeb(mbase, MUSB_TESTMODE,
770 case MUSB_EP0_STAGE_STATUSOUT:
771 /* end of sequence #1: write to host (TX state) */
773 struct musb_request *req;
775 req = next_ep0_request(musb);
777 musb_g_ep0_giveback(musb, &req->request);
781 * In case when several interrupts can get coalesced,
782 * check to see if we've already received a SETUP packet...
784 if (csr & MUSB_CSR0_RXPKTRDY)
787 retval = IRQ_HANDLED;
788 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
791 case MUSB_EP0_STAGE_IDLE:
793 * This state is typically (but not always) indiscernible
794 * from the status states since the corresponding interrupts
795 * tend to happen within too little period of time (with only
796 * a zero-length packet in between) and so get coalesced...
798 retval = IRQ_HANDLED;
799 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
802 case MUSB_EP0_STAGE_SETUP:
804 if (csr & MUSB_CSR0_RXPKTRDY) {
805 struct usb_ctrlrequest setup;
809 ERR("SETUP packet len %d != 8 ?\n", len);
812 musb_read_setup(musb, &setup);
813 retval = IRQ_HANDLED;
815 /* sometimes the RESET won't be reported */
816 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
819 printk(KERN_NOTICE "%s: peripheral reset "
822 power = musb_readb(mbase, MUSB_POWER);
823 musb->g.speed = (power & MUSB_POWER_HSMODE)
824 ? USB_SPEED_HIGH : USB_SPEED_FULL;
828 switch (musb->ep0_state) {
830 /* sequence #3 (no data stage), includes requests
831 * we can't forward (notably SET_ADDRESS and the
832 * device/endpoint feature set/clear operations)
833 * plus SET_CONFIGURATION and others we must
835 case MUSB_EP0_STAGE_ACKWAIT:
836 handled = service_zero_data_request(
840 * We're expecting no data in any case, so
841 * always set the DATAEND bit -- doing this
842 * here helps avoid SetupEnd interrupt coming
843 * in the idle stage when we're stalling...
845 musb->ackpend |= MUSB_CSR0_P_DATAEND;
847 /* status stage might be immediate */
850 MUSB_EP0_STAGE_STATUSIN;
853 /* sequence #1 (IN to host), includes GET_STATUS
854 * requests that we can't forward, GET_DESCRIPTOR
855 * and others that we must
857 case MUSB_EP0_STAGE_TX:
858 handled = service_in_request(musb, &setup);
860 musb->ackpend = MUSB_CSR0_TXPKTRDY
861 | MUSB_CSR0_P_DATAEND;
863 MUSB_EP0_STAGE_STATUSOUT;
867 /* sequence #2 (OUT from host), always forward */
868 default: /* MUSB_EP0_STAGE_RX */
872 dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
874 decode_ep0stage(musb->ep0_state));
876 /* unless we need to delegate this to the gadget
877 * driver, we know how to wrap this up: csr0 has
878 * not yet been written.
882 else if (handled > 0)
885 handled = forward_to_driver(musb, &setup);
887 musb_ep_select(mbase, 0);
889 dev_dbg(musb->controller, "stall (%d)\n", handled);
890 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
891 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
893 musb_writew(regs, MUSB_CSR0,
900 case MUSB_EP0_STAGE_ACKWAIT:
901 /* This should not happen. But happens with tusb6010 with
902 * g_file_storage and high speed. Do nothing.
904 retval = IRQ_HANDLED;
910 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
911 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
920 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
926 static int musb_g_ep0_disable(struct usb_ep *e)
933 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
936 struct musb_request *req;
939 unsigned long lockflags;
947 regs = musb->control_ep->regs;
949 req = to_musb_request(r);
951 req->request.actual = 0;
952 req->request.status = -EINPROGRESS;
955 spin_lock_irqsave(&musb->lock, lockflags);
957 if (!list_empty(&ep->req_list)) {
962 switch (musb->ep0_state) {
963 case MUSB_EP0_STAGE_RX: /* control-OUT data */
964 case MUSB_EP0_STAGE_TX: /* control-IN data */
965 case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
969 dev_dbg(musb->controller, "ep0 request queued in state %d\n",
975 /* add request to the list */
976 list_add_tail(&req->list, &ep->req_list);
978 dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
979 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
980 req->request.length);
982 musb_ep_select(musb->mregs, 0);
984 /* sequence #1, IN ... start writing the data */
985 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
988 /* sequence #3, no-data ... issue IN status */
989 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
990 if (req->request.length)
993 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
994 musb_writew(regs, MUSB_CSR0,
995 musb->ackpend | MUSB_CSR0_P_DATAEND);
997 musb_g_ep0_giveback(ep->musb, r);
1000 /* else for sequence #2 (OUT), caller provides a buffer
1001 * before the next packet arrives. deferred responses
1002 * (after SETUP is acked) are racey.
1004 } else if (musb->ackpend) {
1005 musb_writew(regs, MUSB_CSR0, musb->ackpend);
1010 spin_unlock_irqrestore(&musb->lock, lockflags);
1014 static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
1016 /* we just won't support this */
1020 static int musb_g_ep0_halt(struct usb_ep *e, int value)
1024 void __iomem *base, *regs;
1025 unsigned long flags;
1035 regs = musb->control_ep->regs;
1038 spin_lock_irqsave(&musb->lock, flags);
1040 if (!list_empty(&ep->req_list)) {
1045 musb_ep_select(base, 0);
1046 csr = musb->ackpend;
1048 switch (musb->ep0_state) {
1050 /* Stalls are usually issued after parsing SETUP packet, either
1051 * directly in irq context from setup() or else later.
1053 case MUSB_EP0_STAGE_TX: /* control-IN data */
1054 case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
1055 case MUSB_EP0_STAGE_RX: /* control-OUT data */
1056 csr = musb_readw(regs, MUSB_CSR0);
1059 /* It's also OK to issue stalls during callbacks when a non-empty
1060 * DATA stage buffer has been read (or even written).
1062 case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
1063 case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
1065 csr |= MUSB_CSR0_P_SENDSTALL;
1066 musb_writew(regs, MUSB_CSR0, csr);
1067 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1071 dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
1076 spin_unlock_irqrestore(&musb->lock, flags);
1080 const struct usb_ep_ops musb_g_ep0_ops = {
1081 .enable = musb_g_ep0_enable,
1082 .disable = musb_g_ep0_disable,
1083 .alloc_request = musb_alloc_request,
1084 .free_request = musb_free_request,
1085 .queue = musb_g_ep0_queue,
1086 .dequeue = musb_g_ep0_dequeue,
1087 .set_halt = musb_g_ep0_halt,