2 * Allwinner SUNXI "glue layer"
4 * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
5 * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
7 * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
8 * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
9 * javen <javen@allwinnertech.com>
11 * Based on the DA8xx "glue layer" code.
12 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
13 * Copyright (C) 2005-2006 by Texas Instruments
15 * This file is part of the Inventra Controller Driver for Linux.
17 * The Inventra Controller Driver for Linux is free software; you
18 * can redistribute it and/or modify it under the terms of the GNU
19 * General Public License version 2 as published by the Free Software
24 #include <asm/arch/cpu.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/usbc.h>
27 #include <asm-generic/gpio.h>
28 #include "linux-compat.h"
29 #include "musb_core.h"
30 #ifdef CONFIG_AXP152_POWER
33 #ifdef CONFIG_AXP209_POWER
36 #ifdef CONFIG_AXP221_POWER
40 /******************************************************************************
41 ******************************************************************************
42 * From the Allwinner driver
43 ******************************************************************************
44 ******************************************************************************/
46 /******************************************************************************
47 * From include/sunxi_usb_bsp.h
48 ******************************************************************************/
51 #define USBC_REG_o_ISCR 0x0400
52 #define USBC_REG_o_PHYCTL 0x0404
53 #define USBC_REG_o_PHYBIST 0x0408
54 #define USBC_REG_o_PHYTUNE 0x040c
56 #define USBC_REG_o_VEND0 0x0043
58 /* Interface Status and Control */
59 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
60 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
61 #define USBC_BP_ISCR_EXT_ID_STATUS 28
62 #define USBC_BP_ISCR_EXT_DM_STATUS 27
63 #define USBC_BP_ISCR_EXT_DP_STATUS 26
64 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
65 #define USBC_BP_ISCR_MERGED_ID_STATUS 24
67 #define USBC_BP_ISCR_ID_PULLUP_EN 17
68 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16
69 #define USBC_BP_ISCR_FORCE_ID 14
70 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12
71 #define USBC_BP_ISCR_VBUS_VALID_SRC 10
73 #define USBC_BP_ISCR_HOSC_EN 7
74 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
75 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5
76 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
77 #define USBC_BP_ISCR_IRQ_ENABLE 3
78 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
79 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
80 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
82 /******************************************************************************
84 ******************************************************************************/
86 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
90 temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
91 temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
92 temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
97 static void USBC_EnableIdPullUp(__iomem void *base)
101 reg_val = musb_readl(base, USBC_REG_o_ISCR);
102 reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
103 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
104 musb_writel(base, USBC_REG_o_ISCR, reg_val);
107 static void USBC_DisableIdPullUp(__iomem void *base)
111 reg_val = musb_readl(base, USBC_REG_o_ISCR);
112 reg_val &= ~(1 << USBC_BP_ISCR_ID_PULLUP_EN);
113 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
114 musb_writel(base, USBC_REG_o_ISCR, reg_val);
117 static void USBC_EnableDpDmPullUp(__iomem void *base)
121 reg_val = musb_readl(base, USBC_REG_o_ISCR);
122 reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
123 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
124 musb_writel(base, USBC_REG_o_ISCR, reg_val);
127 static void USBC_DisableDpDmPullUp(__iomem void *base)
131 reg_val = musb_readl(base, USBC_REG_o_ISCR);
132 reg_val &= ~(1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
133 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
134 musb_writel(base, USBC_REG_o_ISCR, reg_val);
137 static void USBC_ForceIdToLow(__iomem void *base)
141 reg_val = musb_readl(base, USBC_REG_o_ISCR);
142 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
143 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
144 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
145 musb_writel(base, USBC_REG_o_ISCR, reg_val);
148 static void USBC_ForceIdToHigh(__iomem void *base)
152 reg_val = musb_readl(base, USBC_REG_o_ISCR);
153 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
154 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
155 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
156 musb_writel(base, USBC_REG_o_ISCR, reg_val);
159 static void USBC_ForceVbusValidToHigh(__iomem void *base)
163 reg_val = musb_readl(base, USBC_REG_o_ISCR);
164 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
165 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
166 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
167 musb_writel(base, USBC_REG_o_ISCR, reg_val);
170 static void USBC_ConfigFIFO_Base(void)
174 /* config usb fifo, 8kb mode */
175 reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
176 reg_value &= ~(0x03 << 0);
177 reg_value |= (1 << 0);
178 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
181 /******************************************************************************
183 ******************************************************************************/
185 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
187 struct musb *musb = __hci;
188 irqreturn_t retval = IRQ_NONE;
190 /* read and flush interrupts */
191 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
193 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
194 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
196 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
197 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
199 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
201 if (musb->int_usb || musb->int_tx || musb->int_rx)
202 retval |= musb_interrupt(musb);
207 static void sunxi_musb_enable(struct musb *musb)
209 pr_debug("%s():\n", __func__);
211 /* select PIO mode */
212 musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
214 if (is_host_enabled(musb)) {
216 sunxi_usbc_vbus_enable(0);
220 static void sunxi_musb_disable(struct musb *musb)
222 pr_debug("%s():\n", __func__);
224 /* Put the controller back in a pristane state for "usb reset" */
225 if (musb->is_active) {
226 sunxi_usbc_disable(0);
227 sunxi_usbc_enable(0);
232 static int sunxi_musb_init(struct musb *musb)
236 pr_debug("%s():\n", __func__);
238 err = sunxi_usbc_request_resources(0);
242 if (is_host_enabled(musb)) {
243 err = sunxi_usbc_vbus_detect(0);
245 eprintf("Error: A charger is plugged into the OTG\n");
246 sunxi_usbc_free_resources(0);
251 musb->isr = sunxi_musb_interrupt;
252 sunxi_usbc_enable(0);
254 USBC_ConfigFIFO_Base();
255 USBC_EnableDpDmPullUp(musb->mregs);
256 USBC_EnableIdPullUp(musb->mregs);
258 if (is_host_enabled(musb)) {
260 USBC_ForceIdToLow(musb->mregs);
262 /* Peripheral mode */
263 USBC_ForceIdToHigh(musb->mregs);
265 USBC_ForceVbusValidToHigh(musb->mregs);
270 static int sunxi_musb_exit(struct musb *musb)
272 pr_debug("%s():\n", __func__);
274 USBC_DisableDpDmPullUp(musb->mregs);
275 USBC_DisableIdPullUp(musb->mregs);
276 sunxi_usbc_vbus_disable(0);
277 sunxi_usbc_disable(0);
279 return sunxi_usbc_free_resources(0);
282 const struct musb_platform_ops sunxi_musb_ops = {
283 .init = sunxi_musb_init,
284 .exit = sunxi_musb_exit,
286 .enable = sunxi_musb_enable,
287 .disable = sunxi_musb_disable,