5 * Texas Instruments, <www.ti.com>
7 * Author: Dan Murphy <dmurphy@ti.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm-generic/errno.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/sys_proto.h>
19 #include <linux/compat.h>
20 #include <linux/usb/dwc3.h>
21 #include <linux/usb/xhci-omap.h>
23 #include "../host/xhci.h"
25 #ifdef CONFIG_OMAP_USB3PHY1_HOST
26 struct usb_dpll_params {
34 #define NUM_USB_CLKS 6
36 static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
37 {1250, 5, 4, 20, 0}, /* 12 MHz */
38 {3125, 20, 4, 20, 0}, /* 16.8 MHz */
39 {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
40 {1250, 12, 4, 20, 0}, /* 26 MHz */
41 {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
42 {1000, 7, 4, 10, 0}, /* 20 MHz */
45 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
49 writel(SET_PLL_GO, &phy_regs->pll_go);
51 val = readl(&phy_regs->pll_status);
57 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
59 u32 clk_index = get_sys_clk_index();
62 val = readl(&phy_regs->pll_config_1);
63 val &= ~PLL_REGN_MASK;
64 val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
65 writel(val, &phy_regs->pll_config_1);
67 val = readl(&phy_regs->pll_config_2);
68 val &= ~PLL_SELFREQDCO_MASK;
69 val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
70 writel(val, &phy_regs->pll_config_2);
72 val = readl(&phy_regs->pll_config_1);
73 val &= ~PLL_REGM_MASK;
74 val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
75 writel(val, &phy_regs->pll_config_1);
77 val = readl(&phy_regs->pll_config_4);
78 val &= ~PLL_REGM_F_MASK;
79 val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
80 writel(val, &phy_regs->pll_config_4);
82 val = readl(&phy_regs->pll_config_3);
84 val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
85 writel(val, &phy_regs->pll_config_3);
87 omap_usb_dpll_relock(phy_regs);
90 static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
92 u32 rate = get_sys_clk_freq()/1000000;
95 val = readl((*ctrl)->control_phy_power_usb);
96 val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
97 val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
98 val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
100 writel(val, (*ctrl)->control_phy_power_usb);
103 void usb_phy_power(int on)
107 val = readl((*ctrl)->control_phy_power_usb);
109 val &= ~USB3_PWRCTL_CLK_CMD_MASK;
110 val |= USB3_PHY_TX_RX_POWERON;
112 val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
115 writel(val, (*ctrl)->control_phy_power_usb);
118 void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
120 omap_usb_dpll_lock(phy_regs);
121 usb3_phy_partial_powerup(phy_regs);
123 * Give enough time for the PHY to partially power-up before
124 * powering it up completely. delay value suggested by the HW
130 static void omap_enable_usb3_phy(struct omap_xhci *omap)
134 val = (USBOTGSS_DMADISABLE |
135 USBOTGSS_STANDBYMODE_SMRT_WKUP |
136 USBOTGSS_IDLEMODE_NOIDLE);
137 writel(val, &omap->otg_wrapper->sysconfig);
139 /* Clear the utmi OTG status */
140 val = readl(&omap->otg_wrapper->utmi_otg_status);
141 writel(val, &omap->otg_wrapper->utmi_otg_status);
143 /* Enable interrupts */
144 writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
145 val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
146 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
147 USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN |
148 USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN |
149 USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN |
150 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN |
151 USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
152 USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
153 USBOTGSS_IRQ_SET_1_OEVT_EN);
154 writel(val, &omap->otg_wrapper->irqenable_set_1);
156 /* Clear the IRQ status */
157 val = readl(&omap->otg_wrapper->irqstatus_1);
158 writel(val, &omap->otg_wrapper->irqstatus_1);
159 val = readl(&omap->otg_wrapper->irqstatus_0);
160 writel(val, &omap->otg_wrapper->irqstatus_0);
162 #endif /* CONFIG_OMAP_USB3PHY1_HOST */
164 #ifdef CONFIG_OMAP_USB2PHY2_HOST
165 static void omap_enable_usb2_phy2(struct omap_xhci *omap)
169 val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
170 writel(val, (*ctrl)->control_srcomp_north_side);
172 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
173 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
175 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
176 (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
177 OTG_SS_CLKCTRL_MODULEMODE_HW));
179 /* This is an undocumented Reserved register */
183 setbits_le32(reg, val);
186 void usb_phy_power(int on)
190 #endif /* CONFIG_OMAP_USB2PHY2_HOST */
192 #ifdef CONFIG_AM437X_USB2PHY2_HOST
193 static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
195 const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
196 USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
198 writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
199 writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
201 writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
202 writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
205 void usb_phy_power(int on)
210 val = readl(USB1_CTRL);
213 * these bits are re-used on AM437x to power up/down the USB
214 * CM and OTG PHYs, if we don't toggle them, USB will not be
215 * functional on newer silicon revisions
217 val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN);
219 val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN;
222 writel(val, USB1_CTRL);
224 #endif /* CONFIG_AM437X_USB2PHY2_HOST */
226 void omap_enable_phy(struct omap_xhci *omap)
228 #ifdef CONFIG_OMAP_USB2PHY2_HOST
229 omap_enable_usb2_phy2(omap);
232 #ifdef CONFIG_AM437X_USB2PHY2_HOST
233 am437x_enable_usb2_phy2(omap);
236 #ifdef CONFIG_OMAP_USB3PHY1_HOST
237 omap_enable_usb3_phy(omap);
238 omap_usb3_phy_init(omap->usb3_phy);