2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2 of
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
25 #define DeviceRequest \
26 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
27 #define DeviceOutRequest \
28 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
30 #define InterfaceRequest \
31 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
33 #define EndpointRequest \
34 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
35 #define EndpointOutRequest \
36 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
43 uint16_t cr_hciversion;
44 uint32_t cr_hcsparams;
45 uint32_t cr_hccparams;
46 uint8_t cr_hcsp_portrt[8];
54 uint32_t or_ctrldssegment;
55 uint32_t or_periodiclistbase;
56 uint32_t or_asynclistaddr;
57 uint32_t _reserved_[9];
58 uint32_t or_configflag;
59 uint32_t or_portsc[2];
63 #define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current */
64 #define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect */
65 #define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect */
66 #define EHCI_PS_PTC 0x000f0000 /* RW port test control */
67 #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
68 #define EHCI_PS_PO 0x00002000 /* RW port owner */
69 #define EHCI_PS_PP 0x00001000 /* RW,RO port power */
70 #define EHCI_PS_LS 0x00000c00 /* RO line status */
71 #define EHCI_PS_PR 0x00000100 /* RW port reset */
72 #define EHCI_PS_SUSP 0x00000080 /* RW suspend */
73 #define EHCI_PS_FPR 0x00000040 /* RW force port resume */
74 #define EHCI_PS_OCC 0x00000020 /* RWC over current change */
75 #define EHCI_PS_OCA 0x00000010 /* RO over current active */
76 #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
77 #define EHCI_PS_PE 0x00000004 /* RW port enable */
78 #define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
79 #define EHCI_PS_CS 0x00000001 /* RO connect status */
80 #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
82 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
85 * Schedule Interface Space.
87 * IMPORTANT: Software must ensure that no interface data structure
88 * reachable by the EHCI host controller spans a 4K page boundary!
90 * Periodic transfers (i.e. isochronous and interrupt transfers) are
94 /* Queue Element Transfer Descriptor (qTD). */
97 #define QT_NEXT_TERMINATE 1
100 uint32_t qt_buffer[5];
103 /* Queue Head (QH). */
106 #define QH_LINK_TERMINATE 1
107 #define QH_LINK_TYPE_ITD 0
108 #define QH_LINK_TYPE_QH 2
109 #define QH_LINK_TYPE_SITD 4
110 #define QH_LINK_TYPE_FSTN 6
114 struct qTD qh_overlay;
117 /* Low level intit functions */
119 int ehci_hcd_init(void);
120 int ehci_hcd_stop(void);
121 #endif /* USB_EHCI_H */