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[u-boot] / drivers / video / ati_radeon_fb.h
1 #ifndef __ATI_RADEON_FB_H
2 #define __ATI_RADEON_FB_H
3
4 /***************************************************************
5  * Most of the definitions here are adapted right from XFree86 *
6  ***************************************************************/
7
8 /*
9  * Chip families. Must fit in the low 16 bits of a long word
10  */
11 enum radeon_family {
12         CHIP_FAMILY_UNKNOW,
13         CHIP_FAMILY_LEGACY,
14         CHIP_FAMILY_RADEON,
15         CHIP_FAMILY_RV100,
16         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
17         CHIP_FAMILY_RV200,
18         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
19                                  RS250 (IGP 7000) */
20         CHIP_FAMILY_R200,
21         CHIP_FAMILY_RV250,
22         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
23         CHIP_FAMILY_RV280,
24         CHIP_FAMILY_R300,
25         CHIP_FAMILY_R350,
26         CHIP_FAMILY_RV350,
27         CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
28         CHIP_FAMILY_R420,     /* R420/R423/M18 */
29         CHIP_FAMILY_LAST,
30 };
31
32 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
33                                  ((rinfo)->family == CHIP_FAMILY_RV200)  || \
34                                  ((rinfo)->family == CHIP_FAMILY_RS100)  || \
35                                  ((rinfo)->family == CHIP_FAMILY_RS200)  || \
36                                  ((rinfo)->family == CHIP_FAMILY_RV250)  || \
37                                  ((rinfo)->family == CHIP_FAMILY_RV280)  || \
38                                  ((rinfo)->family == CHIP_FAMILY_RS300))
39
40 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
41                                 ((rinfo)->family == CHIP_FAMILY_RV350) || \
42                                 ((rinfo)->family == CHIP_FAMILY_R350)  || \
43                                 ((rinfo)->family == CHIP_FAMILY_RV380) || \
44                                 ((rinfo)->family == CHIP_FAMILY_R420))
45
46 struct radeonfb_info {
47         char name[20];
48
49         struct pci_device_id    pdev;
50         u16                     family;
51
52         u32                     fb_base_bus;
53         u32                     mmio_base_bus;
54
55         void                    *mmio_base;
56         void                    *fb_base;
57
58         u32                     video_ram;
59         u32                     mapped_vram;
60         int                     vram_width;
61         int                     vram_ddr;
62
63         u32                     fb_local_base;
64 };
65
66 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
67 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
68 #define INREG16(addr)           readw((rinfo->mmio_base)+addr)
69 #define OUTREG16(addr,val)      writew(val, (rinfo->mmio_base)+addr)
70 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
71 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
72
73 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
74                        u32 val, u32 mask)
75 {
76         unsigned int tmp;
77
78         tmp = INREG(addr);
79         tmp &= (mask);
80         tmp |= (val);
81         OUTREG(addr, tmp);
82 }
83
84 #define OUTREGP(addr,val,mask)  _OUTREGP(rinfo, addr, val,mask)
85
86 /*
87  * 2D Engine helper routines
88  */
89 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
90 {
91         int i;
92
93         /* initiate flush */
94         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
95                 ~RB2D_DC_FLUSH_ALL);
96
97         for (i=0; i < 2000000; i++) {
98                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
99                         return;
100                 udelay(1);
101         }
102         printf("radeonfb: Flush Timeout !\n");
103 }
104
105 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
106 {
107         int i;
108
109         for (i=0; i<2000000; i++) {
110                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
111                         return;
112                 udelay(1);
113         }
114         printf("radeonfb: FIFO Timeout !\n");
115 }
116
117 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
118 {
119         int i;
120
121         /* ensure FIFO is empty before waiting for idle */
122         _radeon_fifo_wait (rinfo, 64);
123
124         for (i=0; i<2000000; i++) {
125                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
126                         radeon_engine_flush (rinfo);
127                         return;
128                 }
129                 udelay(1);
130         }
131         printf("radeonfb: Idle Timeout !\n");
132 }
133
134 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
135 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
136 #define radeon_msleep(ms)               _radeon_msleep(rinfo,ms)
137
138 /*
139  * This structure contains the various registers manipulated by this
140  * driver for setting or restoring a mode. It's mostly copied from
141  * XFree's RADEONSaveRec structure. A few chip settings might still be
142  * tweaked without beeing reflected or saved in these registers though
143  */
144 struct radeon_regs {
145         /* Common registers */
146         u32             ovr_clr;
147         u32             ovr_wid_left_right;
148         u32             ovr_wid_top_bottom;
149         u32             ov0_scale_cntl;
150         u32             mpp_tb_config;
151         u32             mpp_gp_config;
152         u32             subpic_cntl;
153         u32             viph_control;
154         u32             i2c_cntl_1;
155         u32             gen_int_cntl;
156         u32             cap0_trig_cntl;
157         u32             cap1_trig_cntl;
158         u32             bus_cntl;
159         u32             surface_cntl;
160         u32             bios_5_scratch;
161
162         /* Other registers to save for VT switches or driver load/unload */
163         u32             dp_datatype;
164         u32             rbbm_soft_reset;
165         u32             clock_cntl_index;
166         u32             amcgpio_en_reg;
167         u32             amcgpio_mask;
168
169         /* Surface/tiling registers */
170         u32             surf_lower_bound[8];
171         u32             surf_upper_bound[8];
172         u32             surf_info[8];
173
174         /* CRTC registers */
175         u32             crtc_gen_cntl;
176         u32             crtc_ext_cntl;
177         u32             dac_cntl;
178         u32             crtc_h_total_disp;
179         u32             crtc_h_sync_strt_wid;
180         u32             crtc_v_total_disp;
181         u32             crtc_v_sync_strt_wid;
182         u32             crtc_offset;
183         u32             crtc_offset_cntl;
184         u32             crtc_pitch;
185         u32             disp_merge_cntl;
186         u32             grph_buffer_cntl;
187         u32             crtc_more_cntl;
188
189         /* CRTC2 registers */
190         u32             crtc2_gen_cntl;
191         u32             dac2_cntl;
192         u32             disp_output_cntl;
193         u32             disp_hw_debug;
194         u32             disp2_merge_cntl;
195         u32             grph2_buffer_cntl;
196         u32             crtc2_h_total_disp;
197         u32             crtc2_h_sync_strt_wid;
198         u32             crtc2_v_total_disp;
199         u32             crtc2_v_sync_strt_wid;
200         u32             crtc2_offset;
201         u32             crtc2_offset_cntl;
202         u32             crtc2_pitch;
203
204         /* Flat panel regs */
205         u32             fp_crtc_h_total_disp;
206         u32             fp_crtc_v_total_disp;
207         u32             fp_gen_cntl;
208         u32             fp2_gen_cntl;
209         u32             fp_h_sync_strt_wid;
210         u32             fp2_h_sync_strt_wid;
211         u32             fp_horz_stretch;
212         u32             fp_panel_cntl;
213         u32             fp_v_sync_strt_wid;
214         u32             fp2_v_sync_strt_wid;
215         u32             fp_vert_stretch;
216         u32             lvds_gen_cntl;
217         u32             lvds_pll_cntl;
218         u32             tmds_crc;
219         u32             tmds_transmitter_cntl;
220
221         /* Computed values for PLL */
222         u32             dot_clock_freq;
223         int             feedback_div;
224         int             post_div;
225
226         /* PLL registers */
227         u32             ppll_div_3;
228         u32             ppll_ref_div;
229         u32             vclk_ecp_cntl;
230         u32             clk_cntl_index;
231
232         /* Computed values for PLL2 */
233         u32             dot_clock_freq_2;
234         int             feedback_div_2;
235         int             post_div_2;
236
237         /* PLL2 registers */
238         u32             p2pll_ref_div;
239         u32             p2pll_div_0;
240         u32             htotal_cntl2;
241
242         /* Palette */
243         int             palette_valid;
244 };
245
246 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
247 {
248         u32 data;
249
250         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
251         /* radeon_pll_errata_after_index(rinfo); */
252         data = INREG(CLOCK_CNTL_DATA);
253         /* radeon_pll_errata_after_data(rinfo); */
254         return data;
255 }
256
257 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
258                             u32 val)
259 {
260
261         OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
262         /* radeon_pll_errata_after_index(rinfo); */
263         OUTREG(CLOCK_CNTL_DATA, val);
264         /* radeon_pll_errata_after_data(rinfo); */
265 }
266
267 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
268                              u32 val, u32 mask)
269 {
270         unsigned int tmp;
271
272         tmp  = __INPLL(rinfo, index);
273         tmp &= (mask);
274         tmp |= (val);
275         __OUTPLL(rinfo, index, tmp);
276 }
277
278 #define INPLL(addr)                     __INPLL(rinfo, addr)
279 #define OUTPLL(index, val)              __OUTPLL(rinfo, index, val)
280 #define OUTPLLP(index, val, mask)       __OUTPLLP(rinfo, index, val, mask)
281
282 #endif