git.sur5r.net Git - u-boot/blob - drivers/video/atmel_hlcdfb.c

   1 /*
   2  * Driver for AT91/AT32 MULTI LAYER LCD Controller
   3  *
   4  * Copyright (C) 2012 Atmel Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/gpio.h>
  12 #include <asm/arch/clk.h>
  13 #include <lcd.h>
  14 #include <atmel_hlcdc.h>
  15
  16 #if defined(CONFIG_LCD_LOGO)
  17 #include <bmp_logo.h>
  18 #endif
  19
  20 /* configurable parameters */
  21 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  22 #define ATMEL_LCDC_DMA_BURST_LEN        8
  23 #ifndef ATMEL_LCDC_GUARD_TIME
  24 #define ATMEL_LCDC_GUARD_TIME           1
  25 #endif
  26
  27 #define ATMEL_LCDC_FIFO_SIZE            512
  28
  29 #define lcdc_readl(reg)         __raw_readl((reg))
  30 #define lcdc_writel(reg, val)   __raw_writel((val), (reg))
  31
  32 /*
  33  * the CLUT register map as following
  34  * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  35  */
  36 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  37 {
  38         lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  39                 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  40                 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk),
  41                 panel_info.mmio + ATMEL_LCDC_LUT(regno));
  42 }
  43
  44 ushort *configuration_get_cmap(void)
  45 {
  46 #if defined(CONFIG_LCD_LOGO)
  47         return bmp_logo_palette;
  48 #else
  49         return NULL;
  50 #endif
  51 }
  52
  53 void lcd_ctrl_init(void *lcdbase)
  54 {
  55         unsigned long value;
  56         struct lcd_dma_desc *desc;
  57         struct atmel_hlcd_regs *regs;
  58
  59         if (!has_lcdc())
  60                 return;     /* No lcdc */
  61
  62         regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  63
  64         /* Disable DISP signal */
  65         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
  66         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
  67                 udelay(1);
  68         /* Disable synchronization */
  69         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
  70         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
  71                 udelay(1);
  72         /* Disable pixel clock */
  73         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
  74         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
  75                 udelay(1);
  76         /* Disable PWM */
  77         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
  78         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
  79                 udelay(1);
  80
  81         /* Set pixel clock */
  82         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  83         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  84                 value++;
  85
  86         if (value < 1) {
  87                 /* Using system clock as pixel clock */
  88                 lcdc_writel(&regs->lcdc_lcdcfg0,
  89                                         LCDC_LCDCFG0_CLKDIV(0)
  90                                         | LCDC_LCDCFG0_CGDISHCR
  91                                         | LCDC_LCDCFG0_CGDISHEO
  92                                         | LCDC_LCDCFG0_CGDISOVR1
  93                                         | LCDC_LCDCFG0_CGDISBASE
  94                                         | panel_info.vl_clk_pol
  95                                         | LCDC_LCDCFG0_CLKSEL);
  96
  97         } else {
  98                 lcdc_writel(&regs->lcdc_lcdcfg0,
  99                                 LCDC_LCDCFG0_CLKDIV(value - 2)
 100                                 | LCDC_LCDCFG0_CGDISHCR
 101                                 | LCDC_LCDCFG0_CGDISHEO
 102                                 | LCDC_LCDCFG0_CGDISOVR1
 103                                 | LCDC_LCDCFG0_CGDISBASE
 104                                 | panel_info.vl_clk_pol);
 105         }
 106
 107         /* Initialize control register 5 */
 108         value = 0;
 109
 110         value |= panel_info.vl_sync;
 111
 112 #ifndef LCD_OUTPUT_BPP
 113         /* Output is 24bpp */
 114         value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 115 #else
 116         switch (LCD_OUTPUT_BPP) {
 117         case 12:
 118                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 119                 break;
 120         case 16:
 121                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 122                 break;
 123         case 18:
 124                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 125                 break;
 126         case 24:
 127                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 128                 break;
 129         default:
 130                 BUG();
 131                 break;
 132         }
 133 #endif
 134
 135         value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
 136         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 137         lcdc_writel(&regs->lcdc_lcdcfg5, value);
 138
 139         /* Vertical & Horizontal Timing */
 140         value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
 141         value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
 142         lcdc_writel(&regs->lcdc_lcdcfg1, value);
 143
 144         value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
 145         value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
 146         lcdc_writel(&regs->lcdc_lcdcfg2, value);
 147
 148         value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
 149         value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
 150         lcdc_writel(&regs->lcdc_lcdcfg3, value);
 151
 152         /* Display size */
 153         value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
 154         value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
 155         lcdc_writel(&regs->lcdc_lcdcfg4, value);
 156
 157         lcdc_writel(&regs->lcdc_basecfg0,
 158                         LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
 159
 160         switch (NBITS(panel_info.vl_bpix)) {
 161         case 16:
 162                 lcdc_writel(&regs->lcdc_basecfg1,
 163                         LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
 164                 break;
 165         default:
 166                 BUG();
 167                 break;
 168         }
 169
 170         lcdc_writel(&regs->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
 171         lcdc_writel(&regs->lcdc_basecfg3, 0);
 172         lcdc_writel(&regs->lcdc_basecfg4, LCDC_BASECFG4_DMA);
 173
 174         /* Disable all interrupts */
 175         lcdc_writel(&regs->lcdc_lcdidr, ~0UL);
 176         lcdc_writel(&regs->lcdc_baseidr, ~0UL);
 177
 178         /* Setup the DMA descriptor, this descriptor will loop to itself */
 179         desc = (struct lcd_dma_desc *)(lcdbase - 16);
 180
 181         desc->address = (u32)lcdbase;
 182         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 183         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 184                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 185         desc->next = (u32)desc;
 186
 187         /* Flush the DMA descriptor if we enabled dcache */
 188         flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
 189
 190         lcdc_writel(&regs->lcdc_baseaddr, desc->address);
 191         lcdc_writel(&regs->lcdc_basectrl, desc->control);
 192         lcdc_writel(&regs->lcdc_basenext, desc->next);
 193         lcdc_writel(&regs->lcdc_basecher, LCDC_BASECHER_CHEN |
 194                                           LCDC_BASECHER_UPDATEEN);
 195
 196         /* Enable LCD */
 197         value = lcdc_readl(&regs->lcdc_lcden);
 198         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
 199         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
 200                 udelay(1);
 201         value = lcdc_readl(&regs->lcdc_lcden);
 202         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
 203         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
 204                 udelay(1);
 205         value = lcdc_readl(&regs->lcdc_lcden);
 206         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
 207         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
 208                 udelay(1);
 209         value = lcdc_readl(&regs->lcdc_lcden);
 210         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
 211         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
 212                 udelay(1);
 213
 214         /* Enable flushing if we enabled dcache */
 215         lcd_set_flush_dcache(1);
 216 }