2 * Driver for AT91/AT32 LCD Controller
4 * Copyright (C) 2007 Atmel Corporation
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/clk.h>
30 #include <atmel_lcdc.h>
32 /* configurable parameters */
33 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
34 #define ATMEL_LCDC_DMA_BURST_LEN 8
35 #ifndef ATMEL_LCDC_GUARD_TIME
36 #define ATMEL_LCDC_GUARD_TIME 1
39 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9)
40 #define ATMEL_LCDC_FIFO_SIZE 2048
42 #define ATMEL_LCDC_FIFO_SIZE 512
45 #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
46 #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
48 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
50 #if defined(CONFIG_ATMEL_LCD_BGR555)
51 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
52 (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
54 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
55 (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
59 void lcd_ctrl_init(void *lcdbase)
63 /* Turn off the LCD controller and the DMA controller */
64 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
65 ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
67 /* Wait for the LCDC core to become idle */
68 while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
71 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
74 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
76 /* ...set frame size and burst length = 8 words (?) */
77 value = (panel_info.vl_col * panel_info.vl_row *
78 NBITS(panel_info.vl_bpix)) / 32;
79 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
80 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
83 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
84 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
86 value = (value / 2) - 1;
89 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
91 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
92 value << ATMEL_LCDC_CLKVAL_OFFSET);
94 /* Initialize control register 2 */
96 value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
98 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
100 if (panel_info.vl_tft)
101 value |= ATMEL_LCDC_DISTYPE_TFT;
103 value |= panel_info.vl_sync;
104 value |= (panel_info.vl_bpix << 5);
105 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
107 /* Vertical timing */
108 value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
109 value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
110 value |= panel_info.vl_lower_margin;
111 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
113 /* Horizontal timing */
114 value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
115 value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
116 value |= (panel_info.vl_left_margin - 1);
117 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
120 value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
121 value |= panel_info.vl_row - 1;
122 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
124 /* FIFO Threshold: Use formula from data sheet */
125 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
126 lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
128 /* Toggle LCD_MODE every frame */
129 lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
131 /* Disable all interrupts */
132 lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
135 value = ATMEL_LCDC_PS_DIV8 |
136 ATMEL_LCDC_ENA_PWMENABLE;
137 if (!panel_info.vl_cont_pol_low)
138 value |= ATMEL_LCDC_POL_POSITIVE;
139 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
140 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
142 /* Set framebuffer DMA base address and pixel offset */
143 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
145 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
146 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
147 (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
150 ulong calc_fbsize(void)
152 return ((panel_info.vl_col * panel_info.vl_row *
153 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;