2 * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <video_bridge.h>
13 #include "../anx98xx-edp.h"
15 #define DP_MAX_LINK_RATE 0x001
16 #define DP_MAX_LANE_COUNT 0x002
17 #define DP_MAX_LANE_COUNT_MASK 0x1f
23 static int anx6345_write(struct udevice *dev, unsigned int addr_off,
24 unsigned char reg_addr, unsigned char value)
36 ret = dm_i2c_xfer(dev, &msg, 1);
38 debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
39 __func__, reg_addr, value, ret);
46 static int anx6345_read(struct udevice *dev, unsigned int addr_off,
47 unsigned char reg_addr, unsigned char *value)
50 struct i2c_msg msg[2];
53 msg[0].addr = addr_off;
58 msg[1].addr = addr_off;
59 msg[1].flags = I2C_M_RD;
62 ret = dm_i2c_xfer(dev, msg, 2);
64 debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n",
65 __func__, (int)reg_addr, value, ret);
73 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
76 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
78 return anx6345_write(dev, chip->chip_addr, reg_addr, value);
81 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
84 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
86 return anx6345_read(dev, chip->chip_addr, reg_addr, value);
89 static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
92 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
94 return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
97 static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
100 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
102 return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
105 static int anx6345_set_backlight(struct udevice *dev, int percent)
110 static int anx6345_aux_wait(struct udevice *dev)
112 int ret = -ETIMEDOUT;
117 anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);
118 if (!(v & ANX9804_AUX_EN)) {
126 debug("%s: timed out waiting for AUX_EN to clear\n", __func__);
133 anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);
134 if (v & ANX9804_RPLY_RECEIV) {
142 debug("%s: timed out waiting to receive reply\n", __func__);
146 /* Clear RPLY_RECEIV bit */
147 anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);
149 anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);
150 if ((v & ANX9804_AUX_STATUS_MASK) != 0) {
151 debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK);
158 static void anx6345_aux_addr(struct udevice *dev, u32 addr)
163 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);
164 val = (addr >> 8) & 0xff;
165 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);
166 val = (addr >> 16) & 0x0f;
167 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);
170 static int anx6345_aux_transfer(struct udevice *dev, u8 req,
171 u32 addr, u8 *buf, size_t len)
175 u8 ctrl2 = ANX9804_AUX_EN;
181 ctrl1 |= ANX9804_AUX_LENGTH(len);
183 ctrl2 |= ANX9804_ADDR_ONLY;
185 if (len && !(req & ANX9804_AUX_TX_COMM_READ)) {
186 for (i = 0; i < len; i++)
187 anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);
190 anx6345_aux_addr(dev, addr);
191 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
192 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);
193 ret = anx6345_aux_wait(dev);
195 debug("AUX transaction timed out\n");
199 if (len && (req & ANX9804_AUX_TX_COMM_READ)) {
200 for (i = 0; i < len; i++)
201 anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);
207 static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,
208 u8 offset, size_t count, u8 *buf)
214 for (i = 0; i < count; i += 16) {
215 cur_cnt = (count - i) > 16 ? 16 : count - i;
216 cur_offset = offset + i;
217 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,
218 chip_addr, &cur_offset, 1);
220 debug("%s: failed to set i2c offset: %d\n",
224 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,
225 chip_addr, buf + i, cur_cnt);
227 debug("%s: failed to read from i2c device: %d\n",
236 static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
240 ret = anx6345_aux_transfer(dev,
241 ANX9804_AUX_TX_COMM_READ |
242 ANX9804_AUX_TX_COMM_DP_TRANSACTION,
245 debug("Failed to read DPCD\n");
252 static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
254 struct anx6345_priv *priv = dev_get_priv(dev);
256 if (size > EDID_SIZE)
258 memcpy(buf, priv->edid, size);
263 static int anx6345_attach(struct udevice *dev)
269 static int anx6345_enable(struct udevice *dev)
271 u8 chipid, colordepth, lanes, data_rate, c;
273 struct display_timing timing;
274 struct anx6345_priv *priv = dev_get_priv(dev);
276 /* Deassert reset and enable power */
277 ret = video_bridge_set_active(dev, true);
282 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);
284 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);
286 /* Write 0 to the powerdown reg (powerup everything) */
287 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
289 ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);
291 debug("%s: read id failed: %d\n", __func__, ret);
295 debug("ANX63xx detected.\n");
298 debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid);
302 for (i = 0; i < 100; i++) {
303 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
304 anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);
305 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
306 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
312 debug("Error anx6345 clock is not stable\n");
314 /* Set a bunch of analog related register values */
315 anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);
316 anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);
317 anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);
320 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
321 ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
323 /* Power up and configure lanes */
324 anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
325 anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
326 anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
327 anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
328 anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
331 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,
332 ANX9804_RST_CTRL2_AUX);
333 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);
335 /* Powerdown audio and some other unused bits */
336 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
337 anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
338 anx6345_write_r0(dev, 0xa7, 0x00);
340 anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
341 if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
342 debug("Failed to parse EDID\n");
345 debug("%s: panel found: %dx%d, bpp %d\n", __func__,
346 timing.hactive.typ, timing.vactive.typ, bpp);
348 colordepth = 0x00; /* 6 bit */
350 colordepth = 0x10; /* 8 bit */
351 anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);
353 if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {
354 debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__);
357 debug("%s: data_rate: %d\n", __func__, (int)data_rate);
358 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
359 debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__);
362 lanes &= DP_MAX_LANE_COUNT_MASK;
363 debug("%s: lanes: %d\n", __func__, (int)lanes);
365 /* Set data-rate / lanes */
366 anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);
367 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
370 anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,
371 ANX9804_LINK_TRAINING_CTRL_EN);
373 for (i = 0; i < 100; i++) {
374 anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
375 if ((chipid == 0x63) && (c & 0x80) == 0)
381 debug("Error anx6345 link training timeout\n");
386 anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,
387 ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
388 /* Force stream valid */
389 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
390 ANX9804_SYS_CTRL3_F_HPD |
391 ANX9804_SYS_CTRL3_HPD_CTRL |
392 ANX9804_SYS_CTRL3_F_VALID |
393 ANX9804_SYS_CTRL3_VALID_CTRL);
398 static int anx6345_probe(struct udevice *dev)
400 if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
401 return -EPROTONOSUPPORT;
403 return anx6345_enable(dev);
406 struct video_bridge_ops anx6345_ops = {
407 .attach = anx6345_attach,
408 .set_backlight = anx6345_set_backlight,
409 .read_edid = anx6345_read_edid,
412 static const struct udevice_id anx6345_ids[] = {
413 { .compatible = "analogix,anx6345", },
417 U_BOOT_DRIVER(analogix_anx6345) = {
418 .name = "analogix_anx6345",
419 .id = UCLASS_VIDEO_BRIDGE,
420 .of_match = anx6345_ids,
421 .probe = anx6345_probe,
423 .priv_auto_alloc_size = sizeof(struct anx6345_priv),