5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
7 * Copyright (C) 2008-2009 MontaVista Software Inc.
8 * Copyright (C) 2008-2009 Texas Instruments Inc
10 * Based on the LCD driver for TI Avalanche processors written by
11 * Ajay Singh and Shalom Hai.
13 * SPDX-License-Identifier: GPL-2.0+
30 enum raster_load_mode {
35 struct display_panel {
36 enum panel_type panel_type; /* QVGA */
39 enum panel_shade panel_shade;
43 const char name[25]; /* Full name <vendor>_<model> */
45 unsigned short height;
46 int hfp; /* Horizontal front porch */
47 int hbp; /* Horizontal back porch */
48 int hsw; /* Horizontal Sync Pulse Width */
49 int vfp; /* Vertical front porch */
50 int vbp; /* Vertical back porch */
51 int vsw; /* Vertical Sync Pulse Width */
52 unsigned int pxl_clk; /* Pixel clock */
53 unsigned char invert_pxl_clk; /* Invert Pixel clock */
56 struct da8xx_lcdc_platform_data {
57 const char manu_name[10];
58 void *controller_data;
60 void (*panel_power_ctrl)(int);
63 struct lcd_ctrl_config {
64 const struct display_panel *p_disp_panel;
66 /* AC Bias Pin Frequency */
69 /* AC Bias Pin Transitions per Interrupt */
78 /* FIFO DMA Request Delay */
81 /* TFT Alternative Signal Mapping (Only for active) */
82 unsigned char tft_alt_mode;
84 /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
85 unsigned char stn_565_mode;
87 /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
88 unsigned char mono_8bit_mode;
90 /* Invert line clock */
91 unsigned char invert_line_clock;
93 /* Invert frame clock */
94 unsigned char invert_frm_clock;
96 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
97 unsigned char sync_edge;
99 /* Horizontal and Vertical Sync: Control: 0=ignore */
100 unsigned char sync_ctrl;
102 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
103 unsigned char raster_order;
106 struct lcd_sync_arg {
112 void da8xx_video_init(const struct da8xx_panel *panel,
113 const struct lcd_ctrl_config *lcd_cfg,
116 #endif /* ifndef DA8XX_FB_H */