1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Samsung Electronics
5 * Author: Donghwa Lee <dh09.lee@samsung.com>
13 #include <linux/libfdt.h>
15 #include <video_bridge.h>
16 #include <linux/compat.h>
17 #include <linux/err.h>
18 #include <asm/arch/clk.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/dp_info.h>
21 #include <asm/arch/dp.h>
22 #include <asm/arch/pinmux.h>
23 #include <asm/arch/power.h>
25 #include "exynos_dp_lowlevel.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
31 disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
32 disp_info->h_back_porch + disp_info->h_front_porch;
33 disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
34 disp_info->v_back_porch + disp_info->v_front_porch;
39 static int exynos_dp_init_dp(struct exynos_dp *regs)
42 exynos_dp_reset(regs);
44 /* SW defined function Normal operation */
45 exynos_dp_enable_sw_func(regs, DP_ENABLE);
47 ret = exynos_dp_init_analog_func(regs);
48 if (ret != EXYNOS_DP_SUCCESS)
51 exynos_dp_init_hpd(regs);
52 exynos_dp_init_aux(regs);
57 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
60 unsigned char sum = 0;
62 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
63 sum = sum + edid_data[i];
68 static unsigned int exynos_dp_read_edid(struct exynos_dp *regs)
70 unsigned char edid[EDID_BLOCK_LENGTH * 2];
71 unsigned int extend_block = 0;
73 unsigned char test_vector;
77 * EDID device address is 0x50.
78 * However, if necessary, you must have set upper address
79 * into E-EDID in I2C device, 0x30.
82 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
83 exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR,
84 EDID_EXTENSION_FLAG, &extend_block);
86 if (extend_block > 0) {
87 printf("DP EDID data includes a single extension!\n");
90 retval = exynos_dp_read_bytes_from_i2c(regs,
94 &edid[EDID_HEADER_PATTERN]);
96 printf("DP EDID Read failed!\n");
99 sum = exynos_dp_calc_edid_check_sum(edid);
101 printf("DP EDID bad checksum!\n");
105 /* Read additional EDID data */
106 retval = exynos_dp_read_bytes_from_i2c(regs,
107 I2C_EDID_DEVICE_ADDR,
110 &edid[EDID_BLOCK_LENGTH]);
112 printf("DP EDID Read failed!\n");
115 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
117 printf("DP EDID bad checksum!\n");
121 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
123 if (test_vector & DPCD_TEST_EDID_READ) {
124 exynos_dp_write_byte_to_dpcd(regs,
125 DPCD_TEST_EDID_CHECKSUM,
126 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
127 exynos_dp_write_byte_to_dpcd(regs,
129 DPCD_TEST_EDID_CHECKSUM_WRITE);
132 debug("DP EDID data does not include any extensions.\n");
135 retval = exynos_dp_read_bytes_from_i2c(regs,
136 I2C_EDID_DEVICE_ADDR,
139 &edid[EDID_HEADER_PATTERN]);
142 printf("DP EDID Read failed!\n");
145 sum = exynos_dp_calc_edid_check_sum(edid);
147 printf("DP EDID bad checksum!\n");
151 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
153 if (test_vector & DPCD_TEST_EDID_READ) {
154 exynos_dp_write_byte_to_dpcd(regs,
155 DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
156 exynos_dp_write_byte_to_dpcd(regs,
158 DPCD_TEST_EDID_CHECKSUM_WRITE);
162 debug("DP EDID Read success!\n");
167 static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs,
168 struct exynos_dp_priv *priv)
170 unsigned char buf[12];
173 unsigned char retry_cnt;
174 unsigned char dpcd_rev[16];
175 unsigned char lane_bw[16];
176 unsigned char lane_cnt[16];
178 memset(dpcd_rev, 0, 16);
179 memset(lane_bw, 0, 16);
180 memset(lane_cnt, 0, 16);
185 /* Read DPCD 0x0000-0x000b */
186 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12,
188 if (ret != EXYNOS_DP_SUCCESS) {
189 if (retry_cnt == 0) {
190 printf("DP read_byte_from_dpcd() failed\n");
199 temp = buf[DPCD_DPCD_REV];
200 if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
201 priv->dpcd_rev = temp;
203 printf("DP Wrong DPCD Rev : %x\n", temp);
207 temp = buf[DPCD_MAX_LINK_RATE];
208 if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
209 priv->lane_bw = temp;
211 printf("DP Wrong MAX LINK RATE : %x\n", temp);
215 /* Refer VESA Display Port Standard Ver1.1a Page 120 */
216 if (priv->dpcd_rev == DP_DPCD_REV_11) {
217 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
218 if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
223 temp = buf[DPCD_MAX_LANE_COUNT];
227 if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
228 temp == DP_LANE_CNT_4) {
229 priv->lane_cnt = temp;
231 printf("DP Wrong MAX LANE COUNT : %x\n", temp);
235 ret = exynos_dp_read_edid(regs);
236 if (ret != EXYNOS_DP_SUCCESS) {
237 printf("DP exynos_dp_read_edid() failed\n");
244 static void exynos_dp_init_training(struct exynos_dp *regs)
247 * MACRO_RST must be applied after the PLL_LOCK to avoid
248 * the DP inter pair skew issue for at least 10 us
250 exynos_dp_reset_macro(regs);
252 /* All DP analog module power up */
253 exynos_dp_set_analog_power_down(regs, POWER_ALL, 0);
256 static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
257 struct exynos_dp_priv *priv)
259 unsigned char buf[5];
260 unsigned int ret = 0;
262 debug("DP: %s was called\n", __func__);
264 priv->lt_info.lt_status = DP_LT_CR;
265 priv->lt_info.ep_loop = 0;
266 priv->lt_info.cr_loop[0] = 0;
267 priv->lt_info.cr_loop[1] = 0;
268 priv->lt_info.cr_loop[2] = 0;
269 priv->lt_info.cr_loop[3] = 0;
271 /* Set sink to D0 (Sink Not Ready) mode. */
272 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE,
273 DPCD_SET_POWER_STATE_D0);
274 if (ret != EXYNOS_DP_SUCCESS) {
275 printf("DP write_dpcd_byte failed\n");
279 /* Set link rate and count as you want to establish */
280 exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
281 exynos_dp_set_lane_count(regs, priv->lane_cnt);
283 /* Setup RX configuration */
284 buf[0] = priv->lane_bw;
285 buf[1] = priv->lane_cnt;
287 ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf);
288 if (ret != EXYNOS_DP_SUCCESS) {
289 printf("DP write_dpcd_byte failed\n");
293 exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0,
296 /* Set training pattern 1 */
297 exynos_dp_set_training_pattern(regs, TRAINING_PTN1);
299 /* Set RX training pattern */
300 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
302 buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
303 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
304 buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
305 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
306 buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
307 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
308 buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
309 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
311 ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
313 if (ret != EXYNOS_DP_SUCCESS) {
314 printf("DP write_dpcd_byte failed\n");
321 static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
325 exynos_dp_set_training_pattern(regs, DP_NONE);
327 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
328 DPCD_TRAINING_PATTERN_DISABLED);
329 if (ret != EXYNOS_DP_SUCCESS) {
330 printf("DP request_link_training_req failed\n");
337 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
338 struct exynos_dp *regs, unsigned char enable)
343 ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
345 if (ret != EXYNOS_DP_SUCCESS) {
346 printf("DP read_from_dpcd failed\n");
351 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
353 data = DPCD_LN_COUNT_SET(data);
355 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data);
356 if (ret != EXYNOS_DP_SUCCESS) {
357 printf("DP write_to_dpcd failed\n");
365 static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
366 unsigned char enhance_mode)
370 ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
371 if (ret != EXYNOS_DP_SUCCESS) {
372 printf("DP rx_enhance_mode failed\n");
376 exynos_dp_enable_enhanced_mode(regs, enhance_mode);
381 static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
382 struct exynos_dp_priv *priv,
383 unsigned char *status)
386 unsigned char buf[2];
387 unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
388 unsigned char shift_val[DP_LANE_CNT_4] = {0,};
395 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2,
397 if (ret != EXYNOS_DP_SUCCESS) {
398 printf("DP read lane status failed\n");
402 for (i = 0; i < priv->lane_cnt; i++) {
403 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
404 if (lane_stat[0] != lane_stat[i]) {
405 printf("Wrong lane status\n");
410 *status = lane_stat[0];
415 static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
416 unsigned char lane_num, unsigned char *sw, unsigned char *em)
420 unsigned int dpcd_addr;
421 unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
423 /* lane_num value is used as array index, so this range 0 ~ 3 */
424 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
426 ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf);
427 if (ret != EXYNOS_DP_SUCCESS) {
428 printf("DP read adjust request failed\n");
432 *sw = ((buf >> shift_val[lane_num]) & 0x03);
433 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
438 static int exynos_dp_equalizer_err_link(struct exynos_dp *regs,
439 struct exynos_dp_priv *priv)
443 ret = exynos_dp_training_pattern_dis(regs);
444 if (ret != EXYNOS_DP_SUCCESS) {
445 printf("DP training_pattern_disable() failed\n");
446 priv->lt_info.lt_status = DP_LT_FAIL;
449 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
450 if (ret != EXYNOS_DP_SUCCESS) {
451 printf("DP set_enhanced_mode() failed\n");
452 priv->lt_info.lt_status = DP_LT_FAIL;
458 static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
459 struct exynos_dp_priv *priv)
463 if (priv->lane_bw == DP_LANE_BW_2_70) {
464 priv->lane_bw = DP_LANE_BW_1_62;
465 printf("DP Change lane bw to 1.62Gbps\n");
466 priv->lt_info.lt_status = DP_LT_START;
467 ret = EXYNOS_DP_SUCCESS;
469 ret = exynos_dp_training_pattern_dis(regs);
470 if (ret != EXYNOS_DP_SUCCESS)
471 printf("DP training_patter_disable() failed\n");
473 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
474 if (ret != EXYNOS_DP_SUCCESS)
475 printf("DP set_enhanced_mode() failed\n");
477 priv->lt_info.lt_status = DP_LT_FAIL;
483 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
484 struct exynos_dp_priv *priv)
487 unsigned char lane_stat;
488 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
490 unsigned char adj_req_sw;
491 unsigned char adj_req_em;
492 unsigned char buf[5];
494 debug("DP: %s was called\n", __func__);
497 ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
498 if (ret != EXYNOS_DP_SUCCESS) {
499 printf("DP read lane status failed\n");
500 priv->lt_info.lt_status = DP_LT_FAIL;
504 if (lane_stat & DP_LANE_STAT_CR_DONE) {
505 debug("DP clock Recovery training succeed\n");
506 exynos_dp_set_training_pattern(regs, TRAINING_PTN2);
508 for (i = 0; i < priv->lane_cnt; i++) {
509 ret = exynos_dp_read_dpcd_adj_req(regs, i,
510 &adj_req_sw, &adj_req_em);
511 if (ret != EXYNOS_DP_SUCCESS) {
512 priv->lt_info.lt_status = DP_LT_FAIL;
517 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
519 if ((adj_req_sw == VOLTAGE_LEVEL_3)
520 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
521 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
522 MAX_PRE_EMPHASIS_REACH_3;
524 exynos_dp_set_lanex_pre_emphasis(regs,
528 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
529 buf[1] = lt_ctl_val[0];
530 buf[2] = lt_ctl_val[1];
531 buf[3] = lt_ctl_val[2];
532 buf[4] = lt_ctl_val[3];
534 ret = exynos_dp_write_bytes_to_dpcd(regs,
535 DPCD_TRAINING_PATTERN_SET, 5, buf);
536 if (ret != EXYNOS_DP_SUCCESS) {
537 printf("DP write training pattern1 failed\n");
538 priv->lt_info.lt_status = DP_LT_FAIL;
541 priv->lt_info.lt_status = DP_LT_ET;
543 for (i = 0; i < priv->lane_cnt; i++) {
544 lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
546 ret = exynos_dp_read_dpcd_adj_req(regs, i,
547 &adj_req_sw, &adj_req_em);
548 if (ret != EXYNOS_DP_SUCCESS) {
549 printf("DP read adj req failed\n");
550 priv->lt_info.lt_status = DP_LT_FAIL;
554 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
555 (adj_req_em == PRE_EMPHASIS_LEVEL_3))
556 ret = exynos_dp_reduce_link_rate(regs,
559 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
561 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
563 priv->lt_info.cr_loop[i]++;
564 if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP)
565 ret = exynos_dp_reduce_link_rate(
570 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
572 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
573 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
574 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
575 MAX_PRE_EMPHASIS_REACH_3;
577 exynos_dp_set_lanex_pre_emphasis(regs,
581 ret = exynos_dp_write_bytes_to_dpcd(regs,
582 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
583 if (ret != EXYNOS_DP_SUCCESS) {
584 printf("DP write training pattern2 failed\n");
585 priv->lt_info.lt_status = DP_LT_FAIL;
593 static unsigned int exynos_dp_process_equalizer_training(
594 struct exynos_dp *regs, struct exynos_dp_priv *priv)
597 unsigned char lane_stat, adj_req_sw, adj_req_em, i;
598 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
599 unsigned char interlane_aligned = 0;
601 unsigned char f_lane_cnt;
602 unsigned char sink_stat;
606 ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
607 if (ret != EXYNOS_DP_SUCCESS) {
608 printf("DP read lane status failed\n");
609 priv->lt_info.lt_status = DP_LT_FAIL;
613 debug("DP lane stat : %x\n", lane_stat);
615 if (lane_stat & DP_LANE_STAT_CR_DONE) {
616 ret = exynos_dp_read_byte_from_dpcd(regs,
617 DPCD_LN_ALIGN_UPDATED,
619 if (ret != EXYNOS_DP_SUCCESS) {
620 priv->lt_info.lt_status = DP_LT_FAIL;
625 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
627 for (i = 0; i < priv->lane_cnt; i++) {
628 ret = exynos_dp_read_dpcd_adj_req(regs, i,
629 &adj_req_sw, &adj_req_em);
630 if (ret != EXYNOS_DP_SUCCESS) {
631 printf("DP read adj req 1 failed\n");
632 priv->lt_info.lt_status = DP_LT_FAIL;
638 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
640 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
641 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
642 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
643 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
647 if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
648 (lane_stat&DP_LANE_STAT_SYM_LOCK))
649 && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
650 debug("DP Equalizer training succeed\n");
652 f_bw = exynos_dp_get_link_bandwidth(regs);
653 f_lane_cnt = exynos_dp_get_lane_count(regs);
655 debug("DP final BandWidth : %x\n", f_bw);
656 debug("DP final Lane Count : %x\n", f_lane_cnt);
658 priv->lt_info.lt_status = DP_LT_FINISHED;
660 exynos_dp_equalizer_err_link(regs, priv);
663 priv->lt_info.ep_loop++;
665 if (priv->lt_info.ep_loop > MAX_EQ_LOOP) {
666 if (priv->lane_bw == DP_LANE_BW_2_70) {
667 ret = exynos_dp_reduce_link_rate(
670 priv->lt_info.lt_status =
672 exynos_dp_equalizer_err_link(regs,
676 for (i = 0; i < priv->lane_cnt; i++)
677 exynos_dp_set_lanex_pre_emphasis(
678 regs, lt_ctl_val[i], i);
680 ret = exynos_dp_write_bytes_to_dpcd(regs,
681 DPCD_TRAINING_LANE0_SET,
683 if (ret != EXYNOS_DP_SUCCESS) {
684 printf("DP set lt pattern failed\n");
685 priv->lt_info.lt_status =
687 exynos_dp_equalizer_err_link(regs,
692 } else if (priv->lane_bw == DP_LANE_BW_2_70) {
693 ret = exynos_dp_reduce_link_rate(regs, priv);
695 priv->lt_info.lt_status = DP_LT_FAIL;
696 exynos_dp_equalizer_err_link(regs, priv);
702 static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs,
703 struct exynos_dp_priv *priv)
705 unsigned int ret = 0;
706 int training_finished;
708 /* Turn off unnecessary lane */
709 if (priv->lane_cnt == 1)
710 exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1);
712 training_finished = 0;
714 priv->lt_info.lt_status = DP_LT_START;
717 while (!training_finished) {
718 switch (priv->lt_info.lt_status) {
720 ret = exynos_dp_link_start(regs, priv);
721 if (ret != EXYNOS_DP_SUCCESS) {
722 printf("DP LT:link start failed\n");
727 ret = exynos_dp_process_clock_recovery(regs,
729 if (ret != EXYNOS_DP_SUCCESS) {
730 printf("DP LT:clock recovery failed\n");
735 ret = exynos_dp_process_equalizer_training(regs,
737 if (ret != EXYNOS_DP_SUCCESS) {
738 printf("DP LT:equalizer training failed\n");
743 training_finished = 1;
753 static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs,
754 struct exynos_dp_priv *priv)
758 exynos_dp_init_training(regs);
760 ret = exynos_dp_sw_link_training(regs, priv);
761 if (ret != EXYNOS_DP_SUCCESS)
762 printf("DP dp_sw_link_training() failed\n");
767 static void exynos_dp_enable_scramble(struct exynos_dp *regs,
773 exynos_dp_enable_scrambling(regs, DP_ENABLE);
775 exynos_dp_read_byte_from_dpcd(regs,
776 DPCD_TRAINING_PATTERN_SET, &data);
777 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
778 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
780 exynos_dp_enable_scrambling(regs, DP_DISABLE);
781 exynos_dp_read_byte_from_dpcd(regs,
782 DPCD_TRAINING_PATTERN_SET, &data);
783 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
784 (u8)(data | DPCD_SCRAMBLING_DISABLED));
788 static unsigned int exynos_dp_config_video(struct exynos_dp *regs,
789 struct exynos_dp_priv *priv)
791 unsigned int ret = 0;
792 unsigned int retry_cnt;
796 if (priv->video_info.master_mode) {
797 printf("DP does not support master mode\n");
801 exynos_dp_config_video_slave_mode(regs,
805 exynos_dp_set_video_color_format(regs, &priv->video_info);
807 if (priv->video_info.bist_mode) {
808 if (exynos_dp_config_video_bist(regs, priv) != 0)
812 ret = exynos_dp_get_pll_lock_status(regs);
813 if (ret != PLL_LOCKED) {
814 printf("DP PLL is not locked yet\n");
818 if (priv->video_info.master_mode == 0) {
821 ret = exynos_dp_is_slave_video_stream_clock_on(regs);
822 if (ret != EXYNOS_DP_SUCCESS) {
823 if (retry_cnt == 0) {
824 printf("DP stream_clock_on failed\n");
834 /* Set to use the register calculated M/N video */
835 exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0);
837 /* For video bist, Video timing must be generated by register */
838 exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE);
840 /* Enable video bist */
841 if (priv->video_info.bist_pattern != COLOR_RAMP &&
842 priv->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
843 priv->video_info.bist_pattern != COLOR_SQUARE)
844 exynos_dp_enable_video_bist(regs,
845 priv->video_info.bist_mode);
847 exynos_dp_enable_video_bist(regs, DP_DISABLE);
849 /* Disable video mute */
850 exynos_dp_enable_video_mute(regs, DP_DISABLE);
852 /* Configure video Master or Slave mode */
853 exynos_dp_enable_video_master(regs,
854 priv->video_info.master_mode);
857 exynos_dp_start_video(regs);
859 if (priv->video_info.master_mode == 0) {
862 ret = exynos_dp_is_video_stream_on(regs);
863 if (ret != EXYNOS_DP_SUCCESS) {
864 if (retry_cnt == 0) {
865 printf("DP Timeout of video stream\n");
878 static int exynos_dp_ofdata_to_platdata(struct udevice *dev)
880 struct exynos_dp_priv *priv = dev_get_priv(dev);
881 const void *blob = gd->fdt_blob;
882 unsigned int node = dev_of_offset(dev);
885 addr = devfdt_get_addr(dev);
886 if (addr == FDT_ADDR_T_NONE) {
887 debug("Can't get the DP base address\n");
890 priv->regs = (struct exynos_dp *)addr;
891 priv->disp_info.h_res = fdtdec_get_int(blob, node,
893 priv->disp_info.h_sync_width = fdtdec_get_int(blob, node,
894 "samsung,h-sync-width", 0);
895 priv->disp_info.h_back_porch = fdtdec_get_int(blob, node,
896 "samsung,h-back-porch", 0);
897 priv->disp_info.h_front_porch = fdtdec_get_int(blob, node,
898 "samsung,h-front-porch", 0);
899 priv->disp_info.v_res = fdtdec_get_int(blob, node,
901 priv->disp_info.v_sync_width = fdtdec_get_int(blob, node,
902 "samsung,v-sync-width", 0);
903 priv->disp_info.v_back_porch = fdtdec_get_int(blob, node,
904 "samsung,v-back-porch", 0);
905 priv->disp_info.v_front_porch = fdtdec_get_int(blob, node,
906 "samsung,v-front-porch", 0);
907 priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
908 "samsung,v-sync-rate", 0);
910 priv->lt_info.lt_status = fdtdec_get_int(blob, node,
911 "samsung,lt-status", 0);
913 priv->video_info.master_mode = fdtdec_get_int(blob, node,
914 "samsung,master-mode", 0);
915 priv->video_info.bist_mode = fdtdec_get_int(blob, node,
916 "samsung,bist-mode", 0);
917 priv->video_info.bist_pattern = fdtdec_get_int(blob, node,
918 "samsung,bist-pattern", 0);
919 priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
920 "samsung,h-sync-polarity", 0);
921 priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
922 "samsung,v-sync-polarity", 0);
923 priv->video_info.interlaced = fdtdec_get_int(blob, node,
924 "samsung,interlaced", 0);
925 priv->video_info.color_space = fdtdec_get_int(blob, node,
926 "samsung,color-space", 0);
927 priv->video_info.dynamic_range = fdtdec_get_int(blob, node,
928 "samsung,dynamic-range", 0);
929 priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
930 "samsung,ycbcr-coeff", 0);
931 priv->video_info.color_depth = fdtdec_get_int(blob, node,
932 "samsung,color-depth", 0);
936 static int exynos_dp_bridge_init(struct udevice *dev)
938 const int max_tries = 10;
942 debug("%s\n", __func__);
943 ret = video_bridge_attach(dev);
945 debug("video bridge init failed: %d\n", ret);
950 * We need to wait for 90ms after bringing up the bridge since there
951 * is a phantom "high" on the HPD chip during its bootup. The phantom
952 * high comes within 7ms of de-asserting PD and persists for at least
953 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
954 * phantom high makes it hard for us to know when the NXP chip is up.
958 for (num_tries = 0; num_tries < max_tries; num_tries++) {
959 /* Check HPD. If it's high, or we don't have it, all is well */
960 ret = video_bridge_check_attached(dev);
961 if (!ret || ret == -ENOENT)
964 debug("%s: eDP bridge failed to come up; try %d of %d\n",
965 __func__, num_tries, max_tries);
968 /* Immediately go into bridge reset if the hp line is not high */
972 static int exynos_dp_bridge_setup(const void *blob)
974 const int max_tries = 2;
979 /* Configure I2C registers for Parade bridge */
980 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
982 debug("video bridge init failed: %d\n", ret);
986 if (strncmp(dev->driver->name, "parade", 6)) {
987 /* Mux HPHPD to the special hotplug detect mode */
988 exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
991 for (num_tries = 0; num_tries < max_tries; num_tries++) {
992 ret = exynos_dp_bridge_init(dev);
995 if (num_tries == max_tries - 1)
999 * If we're here, the bridge chip failed to initialise.
1000 * Power down the bridge in an attempt to reset.
1002 video_bridge_set_active(dev, false);
1005 * Arbitrarily wait 300ms here with DP_N low. Don't know for
1006 * sure how long we should wait, but we're being paranoid.
1013 int exynos_dp_enable(struct udevice *dev, int panel_bpp,
1014 const struct display_timing *timing)
1016 struct exynos_dp_priv *priv = dev_get_priv(dev);
1017 struct exynos_dp *regs = priv->regs;
1020 debug("%s: start\n", __func__);
1021 exynos_dp_disp_info(&priv->disp_info);
1023 ret = exynos_dp_bridge_setup(gd->fdt_blob);
1024 if (ret && ret != -ENODEV)
1025 printf("LCD bridge failed to enable: %d\n", ret);
1027 exynos_dp_phy_ctrl(1);
1029 ret = exynos_dp_init_dp(regs);
1030 if (ret != EXYNOS_DP_SUCCESS) {
1031 printf("DP exynos_dp_init_dp() failed\n");
1035 ret = exynos_dp_handle_edid(regs, priv);
1036 if (ret != EXYNOS_DP_SUCCESS) {
1037 printf("EDP handle_edid fail\n");
1041 ret = exynos_dp_set_link_train(regs, priv);
1042 if (ret != EXYNOS_DP_SUCCESS) {
1043 printf("DP link training fail\n");
1047 exynos_dp_enable_scramble(regs, DP_ENABLE);
1048 exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE);
1049 exynos_dp_enable_enhanced_mode(regs, DP_ENABLE);
1051 exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
1052 exynos_dp_set_lane_count(regs, priv->lane_cnt);
1054 exynos_dp_init_video(regs);
1055 ret = exynos_dp_config_video(regs, priv);
1056 if (ret != EXYNOS_DP_SUCCESS) {
1057 printf("Exynos DP init failed\n");
1061 debug("Exynos DP init done\n");
1067 static const struct dm_display_ops exynos_dp_ops = {
1068 .enable = exynos_dp_enable,
1071 static const struct udevice_id exynos_dp_ids[] = {
1072 { .compatible = "samsung,exynos5-dp" },
1076 U_BOOT_DRIVER(exynos_dp) = {
1077 .name = "exynos_dp",
1078 .id = UCLASS_DISPLAY,
1079 .of_match = exynos_dp_ids,
1080 .ops = &exynos_dp_ops,
1081 .ofdata_to_platdata = exynos_dp_ofdata_to_platdata,
1082 .priv_auto_alloc_size = sizeof(struct exynos_dp_priv),