git.sur5r.net Git - u-boot/blob - drivers/video/exynos/exynos_dp_lowlevel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Samsung Electronics
   4  *
   5  * Author: Donghwa Lee <dh09.lee@samsung.com>
   6  */
   7
   8 #include <config.h>
   9 #include <common.h>
  10 #include <linux/err.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/dp_info.h>
  13 #include <asm/arch/dp.h>
  14 #include <fdtdec.h>
  15 #include <linux/libfdt.h>
  16 #include "exynos_dp_lowlevel.h"
  17
  18 /* Declare global data pointer */
  19 static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
  20                                          unsigned int enable)
  21 {
  22         unsigned int reg;
  23
  24         reg = readl(&dp_regs->video_ctl1);
  25         reg &= ~VIDEO_EN_MASK;
  26
  27         /* enable video input */
  28         if (enable)
  29                 reg |= VIDEO_EN_MASK;
  30
  31         writel(reg, &dp_regs->video_ctl1);
  32
  33         return;
  34 }
  35
  36 void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
  37 {
  38         /* enable video bist */
  39         unsigned int reg;
  40
  41         reg = readl(&dp_regs->video_ctl4);
  42         reg &= ~VIDEO_BIST_MASK;
  43
  44         /* enable video bist */
  45         if (enable)
  46                 reg |= VIDEO_BIST_MASK;
  47
  48         writel(reg, &dp_regs->video_ctl4);
  49
  50         return;
  51 }
  52
  53 void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
  54 {
  55         unsigned int reg;
  56
  57         reg = readl(&dp_regs->video_ctl1);
  58         reg &= ~(VIDEO_MUTE_MASK);
  59         if (enable)
  60                 reg |= VIDEO_MUTE_MASK;
  61
  62         writel(reg, &dp_regs->video_ctl1);
  63
  64         return;
  65 }
  66
  67
  68 static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
  69 {
  70         unsigned int reg;
  71
  72         /*
  73          * Set termination
  74          * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
  75          * 24M Phy clock, TX digital logic power is 100:1.0625V
  76          */
  77         reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
  78                 SWING_A_30PER_G_NORMAL;
  79         writel(reg, &dp_regs->analog_ctl1);
  80
  81         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  82         writel(reg, &dp_regs->analog_ctl2);
  83
  84         /*
  85          * Set power source for internal clk driver to 1.0625v.
  86          * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
  87          * Set VCO range of PLL +- 0uA
  88          */
  89         reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
  90         writel(reg, &dp_regs->analog_ctl3);
  91
  92         /*
  93          * Set AUX TX terminal resistor to 102 ohm
  94          * Set AUX channel amplitude control
  95          */
  96         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
  97         writel(reg, &dp_regs->pll_filter_ctl1);
  98
  99         /*
 100          * PLL loop filter bandwidth
 101          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 102          * PLL digital power select: 1.2500V
 103          */
 104         reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
 105
 106         writel(reg, &dp_regs->amp_tuning_ctl);
 107
 108         /*
 109          * PLL loop filter bandwidth
 110          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 111          * PLL digital power select: 1.1250V
 112          */
 113         reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
 114         writel(reg, &dp_regs->pll_ctl);
 115 }
 116
 117 static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
 118 {
 119         /* Set interrupt registers to initial states */
 120
 121         /*
 122          * Disable interrupt
 123          * INT pin assertion polarity. It must be configured
 124          * correctly according to ICU setting.
 125          * 1 = assert high, 0 = assert low
 126          */
 127         writel(INT_POL, &dp_regs->int_ctl);
 128
 129         /* Clear pending registers */
 130         writel(0xff, &dp_regs->common_int_sta1);
 131         writel(0xff, &dp_regs->common_int_sta2);
 132         writel(0xff, &dp_regs->common_int_sta3);
 133         writel(0xff, &dp_regs->common_int_sta4);
 134         writel(0xff, &dp_regs->int_sta);
 135
 136         /* 0:mask,1: unmask */
 137         writel(0x00, &dp_regs->int_sta_mask1);
 138         writel(0x00, &dp_regs->int_sta_mask2);
 139         writel(0x00, &dp_regs->int_sta_mask3);
 140         writel(0x00, &dp_regs->int_sta_mask4);
 141         writel(0x00, &dp_regs->int_sta_mask);
 142 }
 143
 144 void exynos_dp_reset(struct exynos_dp *dp_regs)
 145 {
 146         unsigned int reg_func_1;
 147
 148         /* dp tx sw reset */
 149         writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
 150
 151         exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
 152         exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
 153         exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 154
 155         /* software reset */
 156         reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 157                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 158                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 159
 160         writel(reg_func_1, &dp_regs->func_en1);
 161         writel(reg_func_1, &dp_regs->func_en2);
 162
 163         mdelay(1);
 164
 165         exynos_dp_init_analog_param(dp_regs);
 166         exynos_dp_init_interrupt(dp_regs);
 167
 168         return;
 169 }
 170
 171 void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
 172 {
 173         unsigned int reg;
 174
 175         reg = readl(&dp_regs->func_en1);
 176         reg &= ~(SW_FUNC_EN_N);
 177
 178         if (!enable)
 179                 reg |= SW_FUNC_EN_N;
 180
 181         writel(reg, &dp_regs->func_en1);
 182
 183         return;
 184 }
 185
 186 unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
 187                                              unsigned int block, u32 enable)
 188 {
 189         unsigned int reg;
 190
 191         reg = readl(&dp_regs->phy_pd);
 192         switch (block) {
 193         case AUX_BLOCK:
 194                 reg &= ~(AUX_PD);
 195                 if (enable)
 196                         reg |= AUX_PD;
 197                 break;
 198         case CH0_BLOCK:
 199                 reg &= ~(CH0_PD);
 200                 if (enable)
 201                         reg |= CH0_PD;
 202                 break;
 203         case CH1_BLOCK:
 204                 reg &= ~(CH1_PD);
 205                 if (enable)
 206                         reg |= CH1_PD;
 207                 break;
 208         case CH2_BLOCK:
 209                 reg &= ~(CH2_PD);
 210                 if (enable)
 211                         reg |= CH2_PD;
 212                 break;
 213         case CH3_BLOCK:
 214                 reg &= ~(CH3_PD);
 215                 if (enable)
 216                         reg |= CH3_PD;
 217                 break;
 218         case ANALOG_TOTAL:
 219                 reg &= ~PHY_PD;
 220                 if (enable)
 221                         reg |= PHY_PD;
 222                 break;
 223         case POWER_ALL:
 224                 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
 225                         CH3_PD);
 226                 if (enable)
 227                         reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
 228                                 CH2_PD | CH3_PD);
 229                 break;
 230         default:
 231                 printf("DP undefined block number : %d\n",  block);
 232                 return -1;
 233         }
 234
 235         writel(reg, &dp_regs->phy_pd);
 236
 237         return 0;
 238 }
 239
 240 unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
 241 {
 242         unsigned int reg;
 243
 244         reg = readl(&dp_regs->debug_ctl);
 245
 246         if (reg & PLL_LOCK)
 247                 return PLL_LOCKED;
 248         else
 249                 return PLL_UNLOCKED;
 250 }
 251
 252 static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
 253                                     unsigned int enable)
 254 {
 255         unsigned int reg;
 256
 257         reg = readl(&dp_regs->pll_ctl);
 258         reg &= ~(DP_PLL_PD);
 259
 260         if (!enable)
 261                 reg |= DP_PLL_PD;
 262
 263         writel(reg, &dp_regs->pll_ctl);
 264 }
 265
 266 int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
 267 {
 268         int ret = EXYNOS_DP_SUCCESS;
 269         unsigned int retry_cnt = 10;
 270         unsigned int reg;
 271
 272         /* Power On All Analog block */
 273         exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
 274
 275         reg = PLL_LOCK_CHG;
 276         writel(reg, &dp_regs->common_int_sta1);
 277
 278         reg = readl(&dp_regs->debug_ctl);
 279         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 280         writel(reg, &dp_regs->debug_ctl);
 281
 282         /* Assert DP PLL Reset */
 283         reg = readl(&dp_regs->pll_ctl);
 284         reg |= DP_PLL_RESET;
 285         writel(reg, &dp_regs->pll_ctl);
 286
 287         mdelay(1);
 288
 289         /* Deassert DP PLL Reset */
 290         reg = readl(&dp_regs->pll_ctl);
 291         reg &= ~(DP_PLL_RESET);
 292         writel(reg, &dp_regs->pll_ctl);
 293
 294         exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
 295
 296         while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
 297                 mdelay(1);
 298                 retry_cnt--;
 299                 if (retry_cnt == 0) {
 300                         printf("DP dp's pll lock failed : retry : %d\n",
 301                                         retry_cnt);
 302                         return -EINVAL;
 303                 }
 304         }
 305
 306         debug("dp's pll lock success(%d)\n", retry_cnt);
 307
 308         /* Enable Serdes FIFO function and Link symbol clock domain module */
 309         reg = readl(&dp_regs->func_en2);
 310         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 311                 | AUX_FUNC_EN_N);
 312         writel(reg, &dp_regs->func_en2);
 313
 314         return ret;
 315 }
 316
 317 void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
 318 {
 319         unsigned int reg;
 320
 321         /* Clear interrupts related to Hot Plug Detect */
 322         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 323         writel(reg, &dp_regs->common_int_sta4);
 324
 325         reg = INT_HPD;
 326         writel(reg, &dp_regs->int_sta);
 327
 328         reg = readl(&dp_regs->sys_ctl3);
 329         reg &= ~(F_HPD | HPD_CTRL);
 330         writel(reg, &dp_regs->sys_ctl3);
 331
 332         return;
 333 }
 334
 335 static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
 336 {
 337         unsigned int reg;
 338
 339         /* Disable AUX channel module */
 340         reg = readl(&dp_regs->func_en2);
 341         reg |= AUX_FUNC_EN_N;
 342         writel(reg, &dp_regs->func_en2);
 343
 344         return;
 345 }
 346
 347 void exynos_dp_init_aux(struct exynos_dp *dp_regs)
 348 {
 349         unsigned int reg;
 350
 351         /* Clear interrupts related to AUX channel */
 352         reg = RPLY_RECEIV | AUX_ERR;
 353         writel(reg, &dp_regs->int_sta);
 354
 355         exynos_dp_reset_aux(dp_regs);
 356
 357         /* Disable AUX transaction H/W retry */
 358         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
 359                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 360         writel(reg, &dp_regs->aux_hw_retry_ctl);
 361
 362         /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
 363         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 364         writel(reg, &dp_regs->aux_ch_defer_ctl);
 365
 366         /* Enable AUX channel module */
 367         reg = readl(&dp_regs->func_en2);
 368         reg &= ~AUX_FUNC_EN_N;
 369         writel(reg, &dp_regs->func_en2);
 370
 371         return;
 372 }
 373
 374 void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
 375 {
 376         unsigned int reg;
 377
 378         /* 0: mask, 1: unmask */
 379         reg = COMMON_INT_MASK_1;
 380         writel(reg, &dp_regs->common_int_mask1);
 381
 382         reg = COMMON_INT_MASK_2;
 383         writel(reg, &dp_regs->common_int_mask2);
 384
 385         reg = COMMON_INT_MASK_3;
 386         writel(reg, &dp_regs->common_int_mask3);
 387
 388         reg = COMMON_INT_MASK_4;
 389         writel(reg, &dp_regs->common_int_mask4);
 390
 391         reg = INT_STA_MASK;
 392         writel(reg, &dp_regs->int_sta_mask);
 393
 394         return;
 395 }
 396
 397 unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
 398 {
 399         unsigned int reg;
 400
 401         reg = readl(&dp_regs->sys_ctl3);
 402         if (reg & HPD_STATUS)
 403                 return 0;
 404
 405         return -1;
 406 }
 407
 408 unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
 409 {
 410         int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
 411
 412         mdelay(2);
 413
 414         while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
 415                 if (timeout_loop == 0)
 416                         return -EINVAL;
 417                 mdelay(10);
 418                 timeout_loop--;
 419         }
 420
 421         return EXYNOS_DP_SUCCESS;
 422 }
 423
 424 unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
 425 {
 426         unsigned int reg;
 427         unsigned int ret = 0;
 428         unsigned int retry_cnt;
 429
 430         /* Enable AUX CH operation */
 431         reg = readl(&dp_regs->aux_ch_ctl2);
 432         reg |= AUX_EN;
 433         writel(reg, &dp_regs->aux_ch_ctl2);
 434
 435         retry_cnt = 10;
 436         while (retry_cnt) {
 437                 reg = readl(&dp_regs->int_sta);
 438                 if (!(reg & RPLY_RECEIV)) {
 439                         if (retry_cnt == 0) {
 440                                 printf("DP Reply Timeout!!\n");
 441                                 ret = -EAGAIN;
 442                                 return ret;
 443                         }
 444                         mdelay(1);
 445                         retry_cnt--;
 446                 } else
 447                         break;
 448         }
 449
 450         /* Clear interrupt source for AUX CH command reply */
 451         writel(reg, &dp_regs->int_sta);
 452
 453         /* Clear interrupt source for AUX CH access error */
 454         reg = readl(&dp_regs->int_sta);
 455         if (reg & AUX_ERR) {
 456                 printf("DP Aux Access Error\n");
 457                 writel(AUX_ERR, &dp_regs->int_sta);
 458                 ret = -EAGAIN;
 459                 return ret;
 460         }
 461
 462         /* Check AUX CH error access status */
 463         reg = readl(&dp_regs->aux_ch_sta);
 464         if ((reg & AUX_STATUS_MASK) != 0) {
 465                 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
 466                 ret = -EAGAIN;
 467                 return ret;
 468         }
 469
 470         return EXYNOS_DP_SUCCESS;
 471 }
 472
 473 unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
 474                                           unsigned int reg_addr,
 475                                           unsigned char data)
 476 {
 477         unsigned int reg, ret;
 478
 479         /* Clear AUX CH data buffer */
 480         reg = BUF_CLR;
 481         writel(reg, &dp_regs->buffer_data_ctl);
 482
 483         /* Select DPCD device address */
 484         reg = AUX_ADDR_7_0(reg_addr);
 485         writel(reg, &dp_regs->aux_addr_7_0);
 486         reg = AUX_ADDR_15_8(reg_addr);
 487         writel(reg, &dp_regs->aux_addr_15_8);
 488         reg = AUX_ADDR_19_16(reg_addr);
 489         writel(reg, &dp_regs->aux_addr_19_16);
 490
 491         /* Write data buffer */
 492         reg = (unsigned int)data;
 493         writel(reg, &dp_regs->buf_data0);
 494
 495         /*
 496          * Set DisplayPort transaction and write 1 byte
 497          * If bit 3 is 1, DisplayPort transaction.
 498          * If Bit 3 is 0, I2C transaction.
 499          */
 500         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 501         writel(reg, &dp_regs->aux_ch_ctl1);
 502
 503         /* Start AUX transaction */
 504         ret = exynos_dp_start_aux_transaction(dp_regs);
 505         if (ret != EXYNOS_DP_SUCCESS) {
 506                 printf("DP Aux transaction failed\n");
 507                 return ret;
 508         }
 509
 510         return ret;
 511 }
 512
 513 unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
 514                                            unsigned int reg_addr,
 515                                            unsigned char *data)
 516 {
 517         unsigned int reg;
 518         int retval;
 519
 520         /* Clear AUX CH data buffer */
 521         reg = BUF_CLR;
 522         writel(reg, &dp_regs->buffer_data_ctl);
 523
 524         /* Select DPCD device address */
 525         reg = AUX_ADDR_7_0(reg_addr);
 526         writel(reg, &dp_regs->aux_addr_7_0);
 527         reg = AUX_ADDR_15_8(reg_addr);
 528         writel(reg, &dp_regs->aux_addr_15_8);
 529         reg = AUX_ADDR_19_16(reg_addr);
 530         writel(reg, &dp_regs->aux_addr_19_16);
 531
 532         /*
 533          * Set DisplayPort transaction and read 1 byte
 534          * If bit 3 is 1, DisplayPort transaction.
 535          * If Bit 3 is 0, I2C transaction.
 536          */
 537         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 538         writel(reg, &dp_regs->aux_ch_ctl1);
 539
 540         /* Start AUX transaction */
 541         retval = exynos_dp_start_aux_transaction(dp_regs);
 542         if (!retval)
 543                 debug("DP Aux Transaction fail!\n");
 544
 545         /* Read data buffer */
 546         reg = readl(&dp_regs->buf_data0);
 547         *data = (unsigned char)(reg & 0xff);
 548
 549         return retval;
 550 }
 551
 552 unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
 553                                            unsigned int reg_addr,
 554                                            unsigned int count,
 555                                            unsigned char data[])
 556 {
 557         unsigned int reg;
 558         unsigned int start_offset;
 559         unsigned int cur_data_count;
 560         unsigned int cur_data_idx;
 561         unsigned int retry_cnt;
 562         unsigned int ret = 0;
 563
 564         /* Clear AUX CH data buffer */
 565         reg = BUF_CLR;
 566         writel(reg, &dp_regs->buffer_data_ctl);
 567
 568         start_offset = 0;
 569         while (start_offset < count) {
 570                 /* Buffer size of AUX CH is 16 * 4bytes */
 571                 if ((count - start_offset) > 16)
 572                         cur_data_count = 16;
 573                 else
 574                         cur_data_count = count - start_offset;
 575
 576                 retry_cnt = 5;
 577                 while (retry_cnt) {
 578                         /* Select DPCD device address */
 579                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 580                         writel(reg, &dp_regs->aux_addr_7_0);
 581                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 582                         writel(reg, &dp_regs->aux_addr_15_8);
 583                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 584                         writel(reg, &dp_regs->aux_addr_19_16);
 585
 586                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 587                                         cur_data_idx++) {
 588                                 reg = data[start_offset + cur_data_idx];
 589                                 writel(reg, (unsigned int)&dp_regs->buf_data0 +
 590                                                 (4 * cur_data_idx));
 591                         }
 592                         /*
 593                         * Set DisplayPort transaction and write
 594                         * If bit 3 is 1, DisplayPort transaction.
 595                         * If Bit 3 is 0, I2C transaction.
 596                         */
 597                         reg = AUX_LENGTH(cur_data_count) |
 598                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 599                         writel(reg, &dp_regs->aux_ch_ctl1);
 600
 601                         /* Start AUX transaction */
 602                         ret = exynos_dp_start_aux_transaction(dp_regs);
 603                         if (ret != EXYNOS_DP_SUCCESS) {
 604                                 if (retry_cnt == 0) {
 605                                         printf("DP Aux Transaction failed\n");
 606                                         return ret;
 607                                 }
 608                                 retry_cnt--;
 609                         } else
 610                                 break;
 611                 }
 612                 start_offset += cur_data_count;
 613         }
 614
 615         return ret;
 616 }
 617
 618 unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
 619                                             unsigned int reg_addr,
 620                                             unsigned int count,
 621                                             unsigned char data[])
 622 {
 623         unsigned int reg;
 624         unsigned int start_offset;
 625         unsigned int cur_data_count;
 626         unsigned int cur_data_idx;
 627         unsigned int retry_cnt;
 628         unsigned int ret = 0;
 629
 630         /* Clear AUX CH data buffer */
 631         reg = BUF_CLR;
 632         writel(reg, &dp_regs->buffer_data_ctl);
 633
 634         start_offset = 0;
 635         while (start_offset < count) {
 636                 /* Buffer size of AUX CH is 16 * 4bytes */
 637                 if ((count - start_offset) > 16)
 638                         cur_data_count = 16;
 639                 else
 640                         cur_data_count = count - start_offset;
 641
 642                 retry_cnt = 5;
 643                 while (retry_cnt) {
 644                         /* Select DPCD device address */
 645                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 646                         writel(reg, &dp_regs->aux_addr_7_0);
 647                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 648                         writel(reg, &dp_regs->aux_addr_15_8);
 649                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 650                         writel(reg, &dp_regs->aux_addr_19_16);
 651                         /*
 652                          * Set DisplayPort transaction and read
 653                          * If bit 3 is 1, DisplayPort transaction.
 654                          * If Bit 3 is 0, I2C transaction.
 655                          */
 656                         reg = AUX_LENGTH(cur_data_count) |
 657                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 658                         writel(reg, &dp_regs->aux_ch_ctl1);
 659
 660                         /* Start AUX transaction */
 661                         ret = exynos_dp_start_aux_transaction(dp_regs);
 662                         if (ret != EXYNOS_DP_SUCCESS) {
 663                                 if (retry_cnt == 0) {
 664                                         printf("DP Aux Transaction failed\n");
 665                                         return ret;
 666                                 }
 667                                 retry_cnt--;
 668                         } else
 669                                 break;
 670                 }
 671
 672                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 673                                 cur_data_idx++) {
 674                         reg = readl((unsigned int)&dp_regs->buf_data0 +
 675                                         4 * cur_data_idx);
 676                         data[start_offset + cur_data_idx] = (unsigned char)reg;
 677                 }
 678
 679                 start_offset += cur_data_count;
 680         }
 681
 682         return ret;
 683 }
 684
 685 int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
 686                                 unsigned int device_addr, unsigned int reg_addr)
 687 {
 688         unsigned int reg;
 689         int retval;
 690
 691         /* Set EDID device address */
 692         reg = device_addr;
 693         writel(reg, &dp_regs->aux_addr_7_0);
 694         writel(0x0, &dp_regs->aux_addr_15_8);
 695         writel(0x0, &dp_regs->aux_addr_19_16);
 696
 697         /* Set offset from base address of EDID device */
 698         writel(reg_addr, &dp_regs->buf_data0);
 699
 700         /*
 701          * Set I2C transaction and write address
 702          * If bit 3 is 1, DisplayPort transaction.
 703          * If Bit 3 is 0, I2C transaction.
 704          */
 705         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 706                 AUX_TX_COMM_WRITE;
 707         writel(reg, &dp_regs->aux_ch_ctl1);
 708
 709         /* Start AUX transaction */
 710         retval = exynos_dp_start_aux_transaction(dp_regs);
 711         if (retval != 0)
 712                 printf("%s: DP Aux Transaction fail!\n", __func__);
 713
 714         return retval;
 715 }
 716
 717 int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
 718                                  unsigned int device_addr,
 719                                  unsigned int reg_addr, unsigned int *data)
 720 {
 721         unsigned int reg;
 722         int i;
 723         int retval;
 724
 725         for (i = 0; i < 10; i++) {
 726                 /* Clear AUX CH data buffer */
 727                 reg = BUF_CLR;
 728                 writel(reg, &dp_regs->buffer_data_ctl);
 729
 730                 /* Select EDID device */
 731                 retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
 732                                                      reg_addr);
 733                 if (retval != 0) {
 734                         printf("DP Select EDID device fail. retry !\n");
 735                         continue;
 736                 }
 737
 738                 /*
 739                  * Set I2C transaction and read data
 740                  * If bit 3 is 1, DisplayPort transaction.
 741                  * If Bit 3 is 0, I2C transaction.
 742                  */
 743                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 744                         AUX_TX_COMM_READ;
 745                 writel(reg, &dp_regs->aux_ch_ctl1);
 746
 747                 /* Start AUX transaction */
 748                 retval = exynos_dp_start_aux_transaction(dp_regs);
 749                 if (retval != EXYNOS_DP_SUCCESS)
 750                         printf("%s: DP Aux Transaction fail!\n", __func__);
 751         }
 752
 753         /* Read data */
 754         if (retval == 0)
 755                 *data = readl(&dp_regs->buf_data0);
 756
 757         return retval;
 758 }
 759
 760 int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
 761                                   unsigned int device_addr,
 762                                   unsigned int reg_addr, unsigned int count,
 763                                   unsigned char edid[])
 764 {
 765         unsigned int reg;
 766         unsigned int i, j;
 767         unsigned int cur_data_idx;
 768         unsigned int defer = 0;
 769         int retval = 0;
 770
 771         for (i = 0; i < count; i += 16) { /* use 16 burst */
 772                 for (j = 0; j < 100; j++) {
 773                         /* Clear AUX CH data buffer */
 774                         reg = BUF_CLR;
 775                         writel(reg, &dp_regs->buffer_data_ctl);
 776
 777                         /* Set normal AUX CH command */
 778                         reg = readl(&dp_regs->aux_ch_ctl2);
 779                         reg &= ~ADDR_ONLY;
 780                         writel(reg, &dp_regs->aux_ch_ctl2);
 781
 782                         /*
 783                          * If Rx sends defer, Tx sends only reads
 784                          * request without sending addres
 785                          */
 786                         if (!defer)
 787                                 retval = exynos_dp_select_i2c_device(
 788                                         dp_regs, device_addr, reg_addr + i);
 789                         else
 790                                 defer = 0;
 791
 792                         if (retval == EXYNOS_DP_SUCCESS) {
 793                                 /*
 794                                  * Set I2C transaction and write data
 795                                  * If bit 3 is 1, DisplayPort transaction.
 796                                  * If Bit 3 is 0, I2C transaction.
 797                                  */
 798                                 reg = AUX_LENGTH(16) |
 799                                         AUX_TX_COMM_I2C_TRANSACTION |
 800                                         AUX_TX_COMM_READ;
 801                                 writel(reg, &dp_regs->aux_ch_ctl1);
 802
 803                                 /* Start AUX transaction */
 804                                 retval = exynos_dp_start_aux_transaction(
 805                                                         dp_regs);
 806                                 if (retval == 0)
 807                                         break;
 808                                 else
 809                                         printf("DP Aux Transaction fail!\n");
 810                         }
 811                         /* Check if Rx sends defer */
 812                         reg = readl(&dp_regs->aux_rx_comm);
 813                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 814                                 reg == AUX_RX_COMM_I2C_DEFER) {
 815                                 printf("DP Defer: %d\n", reg);
 816                                 defer = 1;
 817                         }
 818                 }
 819
 820                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 821                         reg = readl((unsigned int)&dp_regs->buf_data0
 822                                                  + 4 * cur_data_idx);
 823                         edid[i + cur_data_idx] = (unsigned char)reg;
 824                 }
 825         }
 826
 827         return retval;
 828 }
 829
 830 void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
 831 {
 832         unsigned int reg;
 833
 834         reg = readl(&dp_regs->phy_test);
 835         reg |= MACRO_RST;
 836         writel(reg, &dp_regs->phy_test);
 837
 838         /* 10 us is the minimum Macro reset time. */
 839         mdelay(1);
 840
 841         reg &= ~MACRO_RST;
 842         writel(reg, &dp_regs->phy_test);
 843 }
 844
 845 void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
 846                                   unsigned char bwtype)
 847 {
 848         unsigned int reg;
 849
 850         reg = (unsigned int)bwtype;
 851
 852          /* Set bandwidth to 2.7G or 1.62G */
 853         if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
 854                 writel(reg, &dp_regs->link_bw_set);
 855 }
 856
 857 unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
 858 {
 859         unsigned char ret;
 860         unsigned int reg;
 861
 862         reg = readl(&dp_regs->link_bw_set);
 863         ret = (unsigned char)reg;
 864
 865         return ret;
 866 }
 867
 868 void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
 869 {
 870         unsigned int reg;
 871
 872         reg = (unsigned int)count;
 873
 874         if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
 875                         (count == DP_LANE_CNT_4))
 876                 writel(reg, &dp_regs->lane_count_set);
 877 }
 878
 879 unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
 880 {
 881         return readl(&dp_regs->lane_count_set);
 882 }
 883
 884 unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
 885                                                unsigned char lanecnt)
 886 {
 887         unsigned int reg_list[DP_LANE_CNT_4] = {
 888                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 889                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 890                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 891                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 892         };
 893
 894         return readl(reg_list[lanecnt]);
 895 }
 896
 897 void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
 898                                       unsigned char request_val,
 899                                       unsigned char lanecnt)
 900 {
 901         unsigned int reg_list[DP_LANE_CNT_4] = {
 902                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 903                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 904                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 905                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 906         };
 907
 908         writel(request_val, reg_list[lanecnt]);
 909 }
 910
 911 void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
 912                                      unsigned int level, unsigned char lanecnt)
 913 {
 914         unsigned char i;
 915         unsigned int reg;
 916         unsigned int reg_list[DP_LANE_CNT_4] = {
 917                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 918                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 919                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 920                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 921         };
 922         unsigned int reg_shift[DP_LANE_CNT_4] = {
 923                 PRE_EMPHASIS_SET_0_SHIFT,
 924                 PRE_EMPHASIS_SET_1_SHIFT,
 925                 PRE_EMPHASIS_SET_2_SHIFT,
 926                 PRE_EMPHASIS_SET_3_SHIFT
 927         };
 928
 929         for (i = 0; i < lanecnt; i++) {
 930                 reg = level << reg_shift[i];
 931                 writel(reg, reg_list[i]);
 932         }
 933 }
 934
 935 void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
 936                                     unsigned int pattern)
 937 {
 938         unsigned int reg = 0;
 939
 940         switch (pattern) {
 941         case PRBS7:
 942                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 943                 break;
 944         case D10_2:
 945                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 946                 break;
 947         case TRAINING_PTN1:
 948                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 949                 break;
 950         case TRAINING_PTN2:
 951                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 952                 break;
 953         case DP_NONE:
 954                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
 955                         SW_TRAINING_PATTERN_SET_NORMAL;
 956                 break;
 957         default:
 958                 break;
 959         }
 960
 961         writel(reg, &dp_regs->training_ptn_set);
 962 }
 963
 964 void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
 965                                     unsigned char enable)
 966 {
 967         unsigned int reg;
 968
 969         reg = readl(&dp_regs->sys_ctl4);
 970         reg &= ~ENHANCED;
 971
 972         if (enable)
 973                 reg |= ENHANCED;
 974
 975         writel(reg, &dp_regs->sys_ctl4);
 976 }
 977
 978 void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
 979 {
 980         unsigned int reg;
 981
 982         reg = readl(&dp_regs->training_ptn_set);
 983         reg &= ~(SCRAMBLING_DISABLE);
 984
 985         if (!enable)
 986                 reg |= SCRAMBLING_DISABLE;
 987
 988         writel(reg, &dp_regs->training_ptn_set);
 989 }
 990
 991 int exynos_dp_init_video(struct exynos_dp *dp_regs)
 992 {
 993         unsigned int reg;
 994
 995         /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
 996         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
 997         writel(reg, &dp_regs->common_int_sta1);
 998
 999         /* I_STRM__CLK detect : DE_CTL : Auto detect */
1000         reg &= ~DET_CTRL;
1001         writel(reg, &dp_regs->sys_ctl1);
1002
1003         return 0;
1004 }
1005
1006 void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
1007                                        struct edp_video_info *video_info)
1008 {
1009         unsigned int reg;
1010
1011         /* Video Slave mode setting */
1012         reg = readl(&dp_regs->func_en1);
1013         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1014         reg |= MASTER_VID_FUNC_EN_N;
1015         writel(reg, &dp_regs->func_en1);
1016
1017         /* Configure Interlaced for slave mode video */
1018         reg = readl(&dp_regs->video_ctl10);
1019         reg &= ~INTERACE_SCAN_CFG;
1020         reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1021         writel(reg, &dp_regs->video_ctl10);
1022
1023         /* Configure V sync polarity for slave mode video */
1024         reg = readl(&dp_regs->video_ctl10);
1025         reg &= ~VSYNC_POLARITY_CFG;
1026         reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1027         writel(reg, &dp_regs->video_ctl10);
1028
1029         /* Configure H sync polarity for slave mode video */
1030         reg = readl(&dp_regs->video_ctl10);
1031         reg &= ~HSYNC_POLARITY_CFG;
1032         reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1033         writel(reg, &dp_regs->video_ctl10);
1034
1035         /* Set video mode to slave mode */
1036         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1037         writel(reg, &dp_regs->soc_general_ctl);
1038 }
1039
1040 void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
1041                                       struct edp_video_info *video_info)
1042 {
1043         unsigned int reg;
1044
1045         /* Configure the input color depth, color space, dynamic range */
1046         reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1047                 (video_info->color_depth << IN_BPC_SHIFT) |
1048                 (video_info->color_space << IN_COLOR_F_SHIFT);
1049         writel(reg, &dp_regs->video_ctl2);
1050
1051         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1052         reg = readl(&dp_regs->video_ctl3);
1053         reg &= ~IN_YC_COEFFI_MASK;
1054         if (video_info->ycbcr_coeff)
1055                 reg |= IN_YC_COEFFI_ITU709;
1056         else
1057                 reg |= IN_YC_COEFFI_ITU601;
1058         writel(reg, &dp_regs->video_ctl3);
1059 }
1060
1061 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
1062                                 struct exynos_dp_priv *priv)
1063 {
1064         unsigned int reg;
1065         unsigned int bist_type = 0;
1066         struct edp_video_info video_info = priv->video_info;
1067
1068         /* For master mode, you don't need to set the video format */
1069         if (video_info.master_mode == 0) {
1070                 writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
1071                        &dp_regs->total_ln_cfg_l);
1072                 writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
1073                        &dp_regs->total_ln_cfg_h);
1074                 writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
1075                        &dp_regs->active_ln_cfg_l);
1076                 writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
1077                        &dp_regs->active_ln_cfg_h);
1078                 writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
1079                 writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
1080                 writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
1081
1082                 writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
1083                        &dp_regs->total_pix_cfg_l);
1084                 writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
1085                        &dp_regs->total_pix_cfg_h);
1086                 writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
1087                        &dp_regs->active_pix_cfg_l);
1088                 writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
1089                        &dp_regs->active_pix_cfg_h);
1090                 writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
1091                        &dp_regs->hfp_cfg_l);
1092                 writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
1093                        &dp_regs->hfp_cfg_h);
1094                 writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
1095                        &dp_regs->hsw_cfg_l);
1096                 writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
1097                        &dp_regs->hsw_cfg_h);
1098                 writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
1099                        &dp_regs->hbp_cfg_l);
1100                 writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
1101                        &dp_regs->hbp_cfg_h);
1102
1103                 /*
1104                  * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
1105                  * HSYNC_P_CFG[0] properly
1106                  */
1107                 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
1108                         video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
1109                         video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1110                 writel(reg, &dp_regs->video_ctl10);
1111         }
1112
1113         /* BIST color bar width set--set to each bar is 32 pixel width */
1114         switch (video_info.bist_pattern) {
1115         case COLORBAR_32:
1116                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1117                           BIST_TYPE_COLOR_BAR;
1118                 break;
1119         case COLORBAR_64:
1120                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1121                           BIST_TYPE_COLOR_BAR;
1122                 break;
1123         case WHITE_GRAY_BALCKBAR_32:
1124                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1125                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1126                 break;
1127         case WHITE_GRAY_BALCKBAR_64:
1128                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1129                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1130                 break;
1131         case MOBILE_WHITEBAR_32:
1132                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1133                           BIST_TYPE_MOBILE_WHITE_BAR;
1134                 break;
1135         case MOBILE_WHITEBAR_64:
1136                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1137                           BIST_TYPE_MOBILE_WHITE_BAR;
1138                 break;
1139         default:
1140                 return -1;
1141         }
1142
1143         reg = bist_type;
1144         writel(reg, &dp_regs->video_ctl4);
1145
1146         return 0;
1147 }
1148
1149 unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
1150 {
1151         unsigned int reg;
1152
1153         /* Update Video stream clk detect status */
1154         reg = readl(&dp_regs->sys_ctl1);
1155         writel(reg, &dp_regs->sys_ctl1);
1156
1157         reg = readl(&dp_regs->sys_ctl1);
1158
1159         if (!(reg & DET_STA)) {
1160                 debug("DP Input stream clock not detected.\n");
1161                 return -EIO;
1162         }
1163
1164         return EXYNOS_DP_SUCCESS;
1165 }
1166
1167 void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
1168                                unsigned int m_value, unsigned int n_value)
1169 {
1170         unsigned int reg;
1171
1172         if (type == REGISTER_M) {
1173                 reg = readl(&dp_regs->sys_ctl4);
1174                 reg |= FIX_M_VID;
1175                 writel(reg, &dp_regs->sys_ctl4);
1176                 reg = M_VID0_CFG(m_value);
1177                 writel(reg, &dp_regs->m_vid0);
1178                 reg = M_VID1_CFG(m_value);
1179                 writel(reg, &dp_regs->m_vid1);
1180                 reg = M_VID2_CFG(m_value);
1181                 writel(reg, &dp_regs->m_vid2);
1182
1183                 reg = N_VID0_CFG(n_value);
1184                 writel(reg, &dp_regs->n_vid0);
1185                 reg = N_VID1_CFG(n_value);
1186                 writel(reg, &dp_regs->n_vid1);
1187                 reg = N_VID2_CFG(n_value);
1188                 writel(reg, &dp_regs->n_vid2);
1189         } else  {
1190                 reg = readl(&dp_regs->sys_ctl4);
1191                 reg &= ~FIX_M_VID;
1192                 writel(reg, &dp_regs->sys_ctl4);
1193         }
1194 }
1195
1196 void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
1197                                      unsigned int type)
1198 {
1199         unsigned int reg;
1200
1201         reg = readl(&dp_regs->video_ctl10);
1202         reg &= ~FORMAT_SEL;
1203
1204         if (type != VIDEO_TIMING_FROM_CAPTURE)
1205                 reg |= FORMAT_SEL;
1206
1207         writel(reg, &dp_regs->video_ctl10);
1208 }
1209
1210 void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
1211                                    unsigned int enable)
1212 {
1213         unsigned int reg;
1214
1215         reg = readl(&dp_regs->soc_general_ctl);
1216         if (enable) {
1217                 reg &= ~VIDEO_MODE_MASK;
1218                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1219         } else {
1220                 reg &= ~VIDEO_MODE_MASK;
1221                 reg |= VIDEO_MODE_SLAVE_MODE;
1222         }
1223
1224         writel(reg, &dp_regs->soc_general_ctl);
1225 }
1226
1227 void exynos_dp_start_video(struct exynos_dp *dp_regs)
1228 {
1229         unsigned int reg;
1230
1231         /* Enable Video input and disable Mute */
1232         reg = readl(&dp_regs->video_ctl1);
1233         reg |= VIDEO_EN;
1234         writel(reg, &dp_regs->video_ctl1);
1235 }
1236
1237 unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
1238 {
1239         unsigned int reg;
1240
1241         /* Update STRM_VALID */
1242         reg = readl(&dp_regs->sys_ctl3);
1243         writel(reg, &dp_regs->sys_ctl3);
1244
1245         reg = readl(&dp_regs->sys_ctl3);
1246         if (!(reg & STRM_VALID))
1247                 return -EIO;
1248
1249         return EXYNOS_DP_SUCCESS;
1250 }