2 * Copyright (C) 2012 Samsung Electronics
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/err.h>
26 #include <asm/arch/clk.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/dp_info.h>
29 #include <asm/arch/dp.h>
33 #include "exynos_dp_lowlevel.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 static struct exynos_dp_platform_data *dp_pd;
39 void __exynos_set_dp_phy(unsigned int onoff)
42 void exynos_set_dp_phy(unsigned int onoff)
43 __attribute__((weak, alias("__exynos_set_dp_phy")));
45 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
47 disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
48 disp_info->h_back_porch + disp_info->h_front_porch;
49 disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
50 disp_info->v_back_porch + disp_info->v_front_porch;
55 static int exynos_dp_init_dp(void)
60 /* SW defined function Normal operation */
61 exynos_dp_enable_sw_func(DP_ENABLE);
63 ret = exynos_dp_init_analog_func();
64 if (ret != EXYNOS_DP_SUCCESS)
73 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
76 unsigned char sum = 0;
78 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
79 sum = sum + edid_data[i];
84 static unsigned int exynos_dp_read_edid(void)
86 unsigned char edid[EDID_BLOCK_LENGTH * 2];
87 unsigned int extend_block = 0;
89 unsigned char test_vector;
93 * EDID device address is 0x50.
94 * However, if necessary, you must have set upper address
95 * into E-EDID in I2C device, 0x30.
98 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
99 exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
102 if (extend_block > 0) {
103 printf("DP EDID data includes a single extension!\n");
106 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
109 &edid[EDID_HEADER_PATTERN]);
111 printf("DP EDID Read failed!\n");
114 sum = exynos_dp_calc_edid_check_sum(edid);
116 printf("DP EDID bad checksum!\n");
120 /* Read additional EDID data */
121 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
124 &edid[EDID_BLOCK_LENGTH]);
126 printf("DP EDID Read failed!\n");
129 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
131 printf("DP EDID bad checksum!\n");
135 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
137 if (test_vector & DPCD_TEST_EDID_READ) {
138 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
139 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
140 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
141 DPCD_TEST_EDID_CHECKSUM_WRITE);
144 debug("DP EDID data does not include any extensions.\n");
147 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
150 &edid[EDID_HEADER_PATTERN]);
153 printf("DP EDID Read failed!\n");
156 sum = exynos_dp_calc_edid_check_sum(edid);
158 printf("DP EDID bad checksum!\n");
162 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
164 if (test_vector & DPCD_TEST_EDID_READ) {
165 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
166 edid[EDID_CHECKSUM]);
167 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
168 DPCD_TEST_EDID_CHECKSUM_WRITE);
172 debug("DP EDID Read success!\n");
177 static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
179 unsigned char buf[12];
182 unsigned char retry_cnt;
183 unsigned char dpcd_rev[16];
184 unsigned char lane_bw[16];
185 unsigned char lane_cnt[16];
187 memset(dpcd_rev, 0, 16);
188 memset(lane_bw, 0, 16);
189 memset(lane_cnt, 0, 16);
194 /* Read DPCD 0x0000-0x000b */
195 ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
197 if (ret != EXYNOS_DP_SUCCESS) {
198 if (retry_cnt == 0) {
199 printf("DP read_byte_from_dpcd() failed\n");
208 temp = buf[DPCD_DPCD_REV];
209 if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
210 edp_info->dpcd_rev = temp;
212 printf("DP Wrong DPCD Rev : %x\n", temp);
216 temp = buf[DPCD_MAX_LINK_RATE];
217 if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
218 edp_info->lane_bw = temp;
220 printf("DP Wrong MAX LINK RATE : %x\n", temp);
224 /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */
225 if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
226 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
227 if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
228 edp_info->dpcd_efc = 1;
230 edp_info->dpcd_efc = 0;
232 temp = buf[DPCD_MAX_LANE_COUNT];
233 edp_info->dpcd_efc = 0;
236 if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
237 temp == DP_LANE_CNT_4) {
238 edp_info->lane_cnt = temp;
240 printf("DP Wrong MAX LANE COUNT : %x\n", temp);
244 ret = exynos_dp_read_edid();
245 if (ret != EXYNOS_DP_SUCCESS) {
246 printf("DP exynos_dp_read_edid() failed\n");
253 static void exynos_dp_init_training(void)
256 * MACRO_RST must be applied after the PLL_LOCK to avoid
257 * the DP inter pair skew issue for at least 10 us
259 exynos_dp_reset_macro();
261 /* All DP analog module power up */
262 exynos_dp_set_analog_power_down(POWER_ALL, 0);
265 static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
267 unsigned char buf[5];
268 unsigned int ret = 0;
270 debug("DP: %s was called\n", __func__);
272 edp_info->lt_info.lt_status = DP_LT_CR;
273 edp_info->lt_info.ep_loop = 0;
274 edp_info->lt_info.cr_loop[0] = 0;
275 edp_info->lt_info.cr_loop[1] = 0;
276 edp_info->lt_info.cr_loop[2] = 0;
277 edp_info->lt_info.cr_loop[3] = 0;
279 /* Set sink to D0 (Sink Not Ready) mode. */
280 ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
281 DPCD_SET_POWER_STATE_D0);
282 if (ret != EXYNOS_DP_SUCCESS) {
283 printf("DP write_dpcd_byte failed\n");
287 /* Set link rate and count as you want to establish*/
288 exynos_dp_set_link_bandwidth(edp_info->lane_bw);
289 exynos_dp_set_lane_count(edp_info->lane_cnt);
291 /* Setup RX configuration */
292 buf[0] = edp_info->lane_bw;
293 buf[1] = edp_info->lane_cnt;
295 ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
297 if (ret != EXYNOS_DP_SUCCESS) {
298 printf("DP write_dpcd_byte failed\n");
302 exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
305 /* Set training pattern 1 */
306 exynos_dp_set_training_pattern(TRAINING_PTN1);
308 /* Set RX training pattern */
309 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
311 buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
312 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
313 buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
314 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
315 buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
316 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
317 buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
318 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
320 ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
322 if (ret != EXYNOS_DP_SUCCESS) {
323 printf("DP write_dpcd_byte failed\n");
330 static unsigned int exynos_dp_training_pattern_dis(void)
332 unsigned int ret = EXYNOS_DP_SUCCESS;
334 exynos_dp_set_training_pattern(DP_NONE);
336 ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
337 DPCD_TRAINING_PATTERN_DISABLED);
338 if (ret != EXYNOS_DP_SUCCESS) {
339 printf("DP requst_link_traninig_req failed\n");
346 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
349 unsigned int ret = EXYNOS_DP_SUCCESS;
351 ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
353 if (ret != EXYNOS_DP_SUCCESS) {
354 printf("DP read_from_dpcd failed\n");
359 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
361 data = DPCD_LN_COUNT_SET(data);
363 ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
365 if (ret != EXYNOS_DP_SUCCESS) {
366 printf("DP write_to_dpcd failed\n");
374 static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
376 unsigned int ret = EXYNOS_DP_SUCCESS;
378 ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
379 if (ret != EXYNOS_DP_SUCCESS) {
380 printf("DP rx_enhance_mode failed\n");
384 exynos_dp_enable_enhanced_mode(enhance_mode);
389 static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
390 unsigned char *status)
393 unsigned char buf[2];
394 unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
395 unsigned char shift_val[DP_LANE_CNT_4] = {0,};
402 ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
403 if (ret != EXYNOS_DP_SUCCESS) {
404 printf("DP read lane status failed\n");
408 for (i = 0; i < edp_info->lane_cnt; i++) {
409 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
410 if (lane_stat[0] != lane_stat[i]) {
411 printf("Wrong lane status\n");
416 *status = lane_stat[0];
421 static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
422 unsigned char *sw, unsigned char *em)
424 unsigned int ret = EXYNOS_DP_SUCCESS;
426 unsigned int dpcd_addr;
427 unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
429 /*lane_num value is used as arry index, so this range 0 ~ 3 */
430 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
432 ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
433 if (ret != EXYNOS_DP_SUCCESS) {
434 printf("DP read adjust request failed\n");
438 *sw = ((buf >> shift_val[lane_num]) & 0x03);
439 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
444 static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
448 ret = exynos_dp_training_pattern_dis();
449 if (ret != EXYNOS_DP_SUCCESS) {
450 printf("DP training_patter_disable() failed\n");
451 edp_info->lt_info.lt_status = DP_LT_FAIL;
454 ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
455 if (ret != EXYNOS_DP_SUCCESS) {
456 printf("DP set_enhanced_mode() failed\n");
457 edp_info->lt_info.lt_status = DP_LT_FAIL;
463 static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
467 if (edp_info->lane_bw == DP_LANE_BW_2_70) {
468 edp_info->lane_bw = DP_LANE_BW_1_62;
469 printf("DP Change lane bw to 1.62Gbps\n");
470 edp_info->lt_info.lt_status = DP_LT_START;
471 ret = EXYNOS_DP_SUCCESS;
473 ret = exynos_dp_training_pattern_dis();
474 if (ret != EXYNOS_DP_SUCCESS)
475 printf("DP training_patter_disable() failed\n");
477 ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
478 if (ret != EXYNOS_DP_SUCCESS)
479 printf("DP set_enhanced_mode() failed\n");
481 edp_info->lt_info.lt_status = DP_LT_FAIL;
487 static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
490 unsigned int ret = EXYNOS_DP_SUCCESS;
491 unsigned char lane_stat;
492 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
494 unsigned char adj_req_sw;
495 unsigned char adj_req_em;
496 unsigned char buf[5];
498 debug("DP: %s was called\n", __func__);
501 ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
502 if (ret != EXYNOS_DP_SUCCESS) {
503 printf("DP read lane status failed\n");
504 edp_info->lt_info.lt_status = DP_LT_FAIL;
508 if (lane_stat & DP_LANE_STAT_CR_DONE) {
509 debug("DP clock Recovery training succeed\n");
510 exynos_dp_set_training_pattern(TRAINING_PTN2);
512 for (i = 0; i < edp_info->lane_cnt; i++) {
513 ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
515 if (ret != EXYNOS_DP_SUCCESS) {
516 edp_info->lt_info.lt_status = DP_LT_FAIL;
521 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
523 if ((adj_req_sw == VOLTAGE_LEVEL_3)
524 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
525 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
526 MAX_PRE_EMPHASIS_REACH_3;
528 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
531 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
532 buf[1] = lt_ctl_val[0];
533 buf[2] = lt_ctl_val[1];
534 buf[3] = lt_ctl_val[2];
535 buf[4] = lt_ctl_val[3];
537 ret = exynos_dp_write_bytes_to_dpcd(
538 DPCD_TRAINING_PATTERN_SET, 5, buf);
539 if (ret != EXYNOS_DP_SUCCESS) {
540 printf("DP write traning pattern1 failed\n");
541 edp_info->lt_info.lt_status = DP_LT_FAIL;
544 edp_info->lt_info.lt_status = DP_LT_ET;
546 for (i = 0; i < edp_info->lane_cnt; i++) {
547 lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
548 ret = exynos_dp_read_dpcd_adj_req(i,
549 &adj_req_sw, &adj_req_em);
550 if (ret != EXYNOS_DP_SUCCESS) {
551 printf("DP read adj req failed\n");
552 edp_info->lt_info.lt_status = DP_LT_FAIL;
556 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
557 (adj_req_em == PRE_EMPHASIS_LEVEL_3))
558 ret = exynos_dp_reduce_link_rate(edp_info);
560 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
562 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
564 edp_info->lt_info.cr_loop[i]++;
565 if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
566 ret = exynos_dp_reduce_link_rate(
571 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
573 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
574 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
575 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
576 MAX_PRE_EMPHASIS_REACH_3;
578 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
581 ret = exynos_dp_write_bytes_to_dpcd(
582 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
583 if (ret != EXYNOS_DP_SUCCESS) {
584 printf("DP write traning pattern2 failed\n");
585 edp_info->lt_info.lt_status = DP_LT_FAIL;
593 static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
596 unsigned int ret = EXYNOS_DP_SUCCESS;
597 unsigned char lane_stat, adj_req_sw, adj_req_em, i;
598 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
599 unsigned char interlane_aligned = 0;
601 unsigned char f_lane_cnt;
602 unsigned char sink_stat;
606 ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
607 if (ret != EXYNOS_DP_SUCCESS) {
608 printf("DP read lane status failed\n");
609 edp_info->lt_info.lt_status = DP_LT_FAIL;
613 debug("DP lane stat : %x\n", lane_stat);
615 if (lane_stat & DP_LANE_STAT_CR_DONE) {
616 ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
618 if (ret != EXYNOS_DP_SUCCESS) {
619 edp_info->lt_info.lt_status = DP_LT_FAIL;
624 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
626 for (i = 0; i < edp_info->lane_cnt; i++) {
627 ret = exynos_dp_read_dpcd_adj_req(i,
628 &adj_req_sw, &adj_req_em);
629 if (ret != EXYNOS_DP_SUCCESS) {
630 printf("DP read adj req 1 failed\n");
631 edp_info->lt_info.lt_status = DP_LT_FAIL;
637 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
639 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
640 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
641 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
642 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
646 if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
647 (lane_stat&DP_LANE_STAT_SYM_LOCK))
648 && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
649 debug("DP Equalizer training succeed\n");
651 f_bw = exynos_dp_get_link_bandwidth();
652 f_lane_cnt = exynos_dp_get_lane_count();
654 debug("DP final BandWidth : %x\n", f_bw);
655 debug("DP final Lane Count : %x\n", f_lane_cnt);
657 edp_info->lt_info.lt_status = DP_LT_FINISHED;
659 exynos_dp_equalizer_err_link(edp_info);
662 edp_info->lt_info.ep_loop++;
664 if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
665 if (edp_info->lane_bw == DP_LANE_BW_2_70) {
666 ret = exynos_dp_reduce_link_rate(
669 edp_info->lt_info.lt_status =
671 exynos_dp_equalizer_err_link(edp_info);
674 for (i = 0; i < edp_info->lane_cnt; i++)
675 exynos_dp_set_lanex_pre_emphasis(
678 ret = exynos_dp_write_bytes_to_dpcd(
679 DPCD_TRAINING_LANE0_SET,
681 if (ret != EXYNOS_DP_SUCCESS) {
682 printf("DP set lt pattern failed\n");
683 edp_info->lt_info.lt_status =
685 exynos_dp_equalizer_err_link(edp_info);
689 } else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
690 ret = exynos_dp_reduce_link_rate(edp_info);
692 edp_info->lt_info.lt_status = DP_LT_FAIL;
693 exynos_dp_equalizer_err_link(edp_info);
699 static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
701 unsigned int ret = 0;
702 int training_finished;
704 /* Turn off unnecessary lane */
705 if (edp_info->lane_cnt == 1)
706 exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
708 training_finished = 0;
710 edp_info->lt_info.lt_status = DP_LT_START;
713 while (!training_finished) {
714 switch (edp_info->lt_info.lt_status) {
716 ret = exynos_dp_link_start(edp_info);
717 if (ret != EXYNOS_DP_SUCCESS) {
718 printf("DP LT:link start failed\n");
723 ret = exynos_dp_process_clock_recovery(edp_info);
724 if (ret != EXYNOS_DP_SUCCESS) {
725 printf("DP LT:clock recovery failed\n");
730 ret = exynos_dp_process_equalizer_training(edp_info);
731 if (ret != EXYNOS_DP_SUCCESS) {
732 printf("DP LT:equalizer training failed\n");
737 training_finished = 1;
747 static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
751 exynos_dp_init_training();
753 ret = exynos_dp_sw_link_training(edp_info);
754 if (ret != EXYNOS_DP_SUCCESS)
755 printf("DP dp_sw_link_traning() failed\n");
760 static void exynos_dp_enable_scramble(unsigned int enable)
765 exynos_dp_enable_scrambling(DP_ENABLE);
767 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
769 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
770 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
772 exynos_dp_enable_scrambling(DP_DISABLE);
773 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
775 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
776 (u8)(data | DPCD_SCRAMBLING_DISABLED));
780 static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
782 unsigned int ret = 0;
783 unsigned int retry_cnt;
787 if (edp_info->video_info.master_mode) {
788 printf("DP does not support master mode\n");
792 exynos_dp_config_video_slave_mode(&edp_info->video_info);
795 exynos_dp_set_video_color_format(&edp_info->video_info);
797 if (edp_info->video_info.bist_mode) {
798 if (exynos_dp_config_video_bist(edp_info) != 0)
802 ret = exynos_dp_get_pll_lock_status();
803 if (ret != PLL_LOCKED) {
804 printf("DP PLL is not locked yet\n");
808 if (edp_info->video_info.master_mode == 0) {
811 ret = exynos_dp_is_slave_video_stream_clock_on();
812 if (ret != EXYNOS_DP_SUCCESS) {
813 if (retry_cnt == 0) {
814 printf("DP stream_clock_on failed\n");
824 /* Set to use the register calculated M/N video */
825 exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
827 /* For video bist, Video timing must be generated by register */
828 exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
830 /* Enable video bist */
831 if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
832 edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
833 edp_info->video_info.bist_pattern != COLOR_SQUARE)
834 exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
836 exynos_dp_enable_video_bist(DP_DISABLE);
838 /* Disable video mute */
839 exynos_dp_enable_video_mute(DP_DISABLE);
841 /* Configure video Master or Slave mode */
842 exynos_dp_enable_video_master(edp_info->video_info.master_mode);
845 exynos_dp_start_video();
847 if (edp_info->video_info.master_mode == 0) {
850 ret = exynos_dp_is_video_stream_on();
851 if (ret != EXYNOS_DP_SUCCESS) {
852 if (retry_cnt == 0) {
853 printf("DP Timeout of video stream\n");
866 #ifdef CONFIG_OF_CONTROL
867 int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
869 unsigned int node = fdtdec_next_compatible(blob, 0,
870 COMPAT_SAMSUNG_EXYNOS5_DP);
872 debug("exynos_dp: Can't get device node for dp\n");
876 edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
878 edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
879 "samsung,h-sync-width", 0);
880 edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
881 "samsung,h-back-porch", 0);
882 edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
883 "samsung,h-front-porch", 0);
884 edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
886 edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
887 "samsung,v-sync-width", 0);
888 edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
889 "samsung,v-back-porch", 0);
890 edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
891 "samsung,v-front-porch", 0);
892 edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
893 "samsung,v-sync-rate", 0);
895 edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
896 "samsung,lt-status", 0);
898 edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
899 "samsung,master-mode", 0);
900 edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
901 "samsung,bist-mode", 0);
902 edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
903 "samsung,bist-pattern", 0);
904 edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
905 "samsung,h-sync-polarity", 0);
906 edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
907 "samsung,v-sync-polarity", 0);
908 edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
909 "samsung,interlaced", 0);
910 edp_info->video_info.color_space = fdtdec_get_int(blob, node,
911 "samsung,color-space", 0);
912 edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
913 "samsung,dynamic-range", 0);
914 edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
915 "samsung,ycbcr-coeff", 0);
916 edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
917 "samsung,color-depth", 0);
922 unsigned int exynos_init_dp(void)
925 struct edp_device_info *edp_info;
927 edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
929 debug("failed to allocate edp device object.\n");
933 #ifdef CONFIG_OF_CONTROL
934 if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
935 debug("unable to parse DP DT node\n");
937 edp_info = dp_pd->edp_dev_info;
938 if (edp_info == NULL) {
939 debug("failed to get edp_info data.\n");
944 exynos_dp_set_base_addr();
946 exynos_dp_disp_info(&edp_info->disp_info);
948 exynos_set_dp_phy(1);
950 ret = exynos_dp_init_dp();
951 if (ret != EXYNOS_DP_SUCCESS) {
952 printf("DP exynos_dp_init_dp() failed\n");
956 ret = exynos_dp_handle_edid(edp_info);
957 if (ret != EXYNOS_DP_SUCCESS) {
958 printf("EDP handle_edid fail\n");
962 ret = exynos_dp_set_link_train(edp_info);
963 if (ret != EXYNOS_DP_SUCCESS) {
964 printf("DP link training fail\n");
968 exynos_dp_enable_scramble(DP_ENABLE);
969 exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
970 exynos_dp_enable_enhanced_mode(DP_ENABLE);
972 exynos_dp_set_link_bandwidth(edp_info->lane_bw);
973 exynos_dp_set_lane_count(edp_info->lane_cnt);
975 exynos_dp_init_video();
976 ret = exynos_dp_config_video(edp_info);
977 if (ret != EXYNOS_DP_SUCCESS) {
978 printf("Exynos DP init failed\n");
982 printf("Exynos DP init done\n");
987 void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd)
990 debug("pd is NULL\n");