2 * Copyright (C) 2012 Samsung Electronics
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/err.h>
26 #include <asm/arch/clk.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/dp_info.h>
29 #include <asm/arch/dp.h>
31 #include "exynos_dp_lowlevel.h"
33 static struct exynos_dp_platform_data *dp_pd;
35 void __exynos_set_dp_phy(unsigned int onoff)
38 void exynos_set_dp_phy(unsigned int onoff)
39 __attribute__((weak, alias("__exynos_set_dp_phy")));
41 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
43 disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
44 disp_info->h_back_porch + disp_info->h_front_porch;
45 disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
46 disp_info->v_back_porch + disp_info->v_front_porch;
51 static int exynos_dp_init_dp(void)
56 /* SW defined function Normal operation */
57 exynos_dp_enable_sw_func(DP_ENABLE);
59 ret = exynos_dp_init_analog_func();
60 if (ret != EXYNOS_DP_SUCCESS)
69 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
72 unsigned char sum = 0;
74 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
75 sum = sum + edid_data[i];
80 static unsigned int exynos_dp_read_edid(void)
82 unsigned char edid[EDID_BLOCK_LENGTH * 2];
83 unsigned int extend_block = 0;
85 unsigned char test_vector;
89 * EDID device address is 0x50.
90 * However, if necessary, you must have set upper address
91 * into E-EDID in I2C device, 0x30.
94 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
95 exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
98 if (extend_block > 0) {
99 printf("DP EDID data includes a single extension!\n");
102 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
105 &edid[EDID_HEADER_PATTERN]);
107 printf("DP EDID Read failed!\n");
110 sum = exynos_dp_calc_edid_check_sum(edid);
112 printf("DP EDID bad checksum!\n");
116 /* Read additional EDID data */
117 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
120 &edid[EDID_BLOCK_LENGTH]);
122 printf("DP EDID Read failed!\n");
125 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
127 printf("DP EDID bad checksum!\n");
131 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
133 if (test_vector & DPCD_TEST_EDID_READ) {
134 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
135 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
136 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
137 DPCD_TEST_EDID_CHECKSUM_WRITE);
140 debug("DP EDID data does not include any extensions.\n");
143 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
146 &edid[EDID_HEADER_PATTERN]);
149 printf("DP EDID Read failed!\n");
152 sum = exynos_dp_calc_edid_check_sum(edid);
154 printf("DP EDID bad checksum!\n");
158 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
160 if (test_vector & DPCD_TEST_EDID_READ) {
161 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
162 edid[EDID_CHECKSUM]);
163 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
164 DPCD_TEST_EDID_CHECKSUM_WRITE);
168 debug("DP EDID Read success!\n");
173 static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
175 unsigned char buf[12];
178 unsigned char retry_cnt;
179 unsigned char dpcd_rev[16];
180 unsigned char lane_bw[16];
181 unsigned char lane_cnt[16];
183 memset(dpcd_rev, 0, 16);
184 memset(lane_bw, 0, 16);
185 memset(lane_cnt, 0, 16);
190 /* Read DPCD 0x0000-0x000b */
191 ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
193 if (ret != EXYNOS_DP_SUCCESS) {
194 if (retry_cnt == 0) {
195 printf("DP read_byte_from_dpcd() failed\n");
204 temp = buf[DPCD_DPCD_REV];
205 if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
206 edp_info->dpcd_rev = temp;
208 printf("DP Wrong DPCD Rev : %x\n", temp);
212 temp = buf[DPCD_MAX_LINK_RATE];
213 if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
214 edp_info->lane_bw = temp;
216 printf("DP Wrong MAX LINK RATE : %x\n", temp);
220 /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */
221 if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
222 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
223 if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
224 edp_info->dpcd_efc = 1;
226 edp_info->dpcd_efc = 0;
228 temp = buf[DPCD_MAX_LANE_COUNT];
229 edp_info->dpcd_efc = 0;
232 if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
233 temp == DP_LANE_CNT_4) {
234 edp_info->lane_cnt = temp;
236 printf("DP Wrong MAX LANE COUNT : %x\n", temp);
240 ret = exynos_dp_read_edid();
241 if (ret != EXYNOS_DP_SUCCESS) {
242 printf("DP exynos_dp_read_edid() failed\n");
249 static void exynos_dp_init_training(void)
252 * MACRO_RST must be applied after the PLL_LOCK to avoid
253 * the DP inter pair skew issue for at least 10 us
255 exynos_dp_reset_macro();
257 /* All DP analog module power up */
258 exynos_dp_set_analog_power_down(POWER_ALL, 0);
261 static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
263 unsigned char buf[5];
264 unsigned int ret = 0;
266 debug("DP: %s was called\n", __func__);
268 edp_info->lt_info.lt_status = DP_LT_CR;
269 edp_info->lt_info.ep_loop = 0;
270 edp_info->lt_info.cr_loop[0] = 0;
271 edp_info->lt_info.cr_loop[1] = 0;
272 edp_info->lt_info.cr_loop[2] = 0;
273 edp_info->lt_info.cr_loop[3] = 0;
275 /* Set sink to D0 (Sink Not Ready) mode. */
276 ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
277 DPCD_SET_POWER_STATE_D0);
278 if (ret != EXYNOS_DP_SUCCESS) {
279 printf("DP write_dpcd_byte failed\n");
283 /* Set link rate and count as you want to establish*/
284 exynos_dp_set_link_bandwidth(edp_info->lane_bw);
285 exynos_dp_set_lane_count(edp_info->lane_cnt);
287 /* Setup RX configuration */
288 buf[0] = edp_info->lane_bw;
289 buf[1] = edp_info->lane_cnt;
291 ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
293 if (ret != EXYNOS_DP_SUCCESS) {
294 printf("DP write_dpcd_byte failed\n");
298 exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
301 /* Set training pattern 1 */
302 exynos_dp_set_training_pattern(TRAINING_PTN1);
304 /* Set RX training pattern */
305 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
307 buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
308 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
309 buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
310 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
311 buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
312 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
313 buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
314 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
316 ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
318 if (ret != EXYNOS_DP_SUCCESS) {
319 printf("DP write_dpcd_byte failed\n");
326 static unsigned int exynos_dp_training_pattern_dis(void)
328 unsigned int ret = EXYNOS_DP_SUCCESS;
330 exynos_dp_set_training_pattern(DP_NONE);
332 ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
333 DPCD_TRAINING_PATTERN_DISABLED);
334 if (ret != EXYNOS_DP_SUCCESS) {
335 printf("DP requst_link_traninig_req failed\n");
342 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
345 unsigned int ret = EXYNOS_DP_SUCCESS;
347 ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
349 if (ret != EXYNOS_DP_SUCCESS) {
350 printf("DP read_from_dpcd failed\n");
355 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
357 data = DPCD_LN_COUNT_SET(data);
359 ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
361 if (ret != EXYNOS_DP_SUCCESS) {
362 printf("DP write_to_dpcd failed\n");
370 static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
372 unsigned int ret = EXYNOS_DP_SUCCESS;
374 ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
375 if (ret != EXYNOS_DP_SUCCESS) {
376 printf("DP rx_enhance_mode failed\n");
380 exynos_dp_enable_enhanced_mode(enhance_mode);
385 static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
386 unsigned char *status)
389 unsigned char buf[2];
390 unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
391 unsigned char shift_val[DP_LANE_CNT_4] = {0,};
398 ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
399 if (ret != EXYNOS_DP_SUCCESS) {
400 printf("DP read lane status failed\n");
404 for (i = 0; i < edp_info->lane_cnt; i++) {
405 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
406 if (lane_stat[0] != lane_stat[i]) {
407 printf("Wrong lane status\n");
412 *status = lane_stat[0];
417 static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
418 unsigned char *sw, unsigned char *em)
420 unsigned int ret = EXYNOS_DP_SUCCESS;
422 unsigned int dpcd_addr;
423 unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
425 /*lane_num value is used as arry index, so this range 0 ~ 3 */
426 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
428 ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
429 if (ret != EXYNOS_DP_SUCCESS) {
430 printf("DP read adjust request failed\n");
434 *sw = ((buf >> shift_val[lane_num]) & 0x03);
435 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
440 static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
444 ret = exynos_dp_training_pattern_dis();
445 if (ret != EXYNOS_DP_SUCCESS) {
446 printf("DP training_patter_disable() failed\n");
447 edp_info->lt_info.lt_status = DP_LT_FAIL;
450 ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
451 if (ret != EXYNOS_DP_SUCCESS) {
452 printf("DP set_enhanced_mode() failed\n");
453 edp_info->lt_info.lt_status = DP_LT_FAIL;
459 static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
463 if (edp_info->lane_bw == DP_LANE_BW_2_70) {
464 edp_info->lane_bw = DP_LANE_BW_1_62;
465 printf("DP Change lane bw to 1.62Gbps\n");
466 edp_info->lt_info.lt_status = DP_LT_START;
467 ret = EXYNOS_DP_SUCCESS;
469 ret = exynos_dp_training_pattern_dis();
470 if (ret != EXYNOS_DP_SUCCESS)
471 printf("DP training_patter_disable() failed\n");
473 ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
474 if (ret != EXYNOS_DP_SUCCESS)
475 printf("DP set_enhanced_mode() failed\n");
477 edp_info->lt_info.lt_status = DP_LT_FAIL;
483 static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
486 unsigned int ret = EXYNOS_DP_SUCCESS;
487 unsigned char lane_stat;
488 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
490 unsigned char adj_req_sw;
491 unsigned char adj_req_em;
492 unsigned char buf[5];
494 debug("DP: %s was called\n", __func__);
497 ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
498 if (ret != EXYNOS_DP_SUCCESS) {
499 printf("DP read lane status failed\n");
500 edp_info->lt_info.lt_status = DP_LT_FAIL;
504 if (lane_stat & DP_LANE_STAT_CR_DONE) {
505 debug("DP clock Recovery training succeed\n");
506 exynos_dp_set_training_pattern(TRAINING_PTN2);
508 for (i = 0; i < edp_info->lane_cnt; i++) {
509 ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
511 if (ret != EXYNOS_DP_SUCCESS) {
512 edp_info->lt_info.lt_status = DP_LT_FAIL;
517 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
519 if ((adj_req_sw == VOLTAGE_LEVEL_3)
520 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
521 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
522 MAX_PRE_EMPHASIS_REACH_3;
524 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
527 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
528 buf[1] = lt_ctl_val[0];
529 buf[2] = lt_ctl_val[1];
530 buf[3] = lt_ctl_val[2];
531 buf[4] = lt_ctl_val[3];
533 ret = exynos_dp_write_bytes_to_dpcd(
534 DPCD_TRAINING_PATTERN_SET, 5, buf);
535 if (ret != EXYNOS_DP_SUCCESS) {
536 printf("DP write traning pattern1 failed\n");
537 edp_info->lt_info.lt_status = DP_LT_FAIL;
540 edp_info->lt_info.lt_status = DP_LT_ET;
542 for (i = 0; i < edp_info->lane_cnt; i++) {
543 lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
544 ret = exynos_dp_read_dpcd_adj_req(i,
545 &adj_req_sw, &adj_req_em);
546 if (ret != EXYNOS_DP_SUCCESS) {
547 printf("DP read adj req failed\n");
548 edp_info->lt_info.lt_status = DP_LT_FAIL;
552 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
553 (adj_req_em == PRE_EMPHASIS_LEVEL_3))
554 ret = exynos_dp_reduce_link_rate(edp_info);
556 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
558 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
560 edp_info->lt_info.cr_loop[i]++;
561 if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
562 ret = exynos_dp_reduce_link_rate(
567 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
569 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
570 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
571 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
572 MAX_PRE_EMPHASIS_REACH_3;
574 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
577 ret = exynos_dp_write_bytes_to_dpcd(
578 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
579 if (ret != EXYNOS_DP_SUCCESS) {
580 printf("DP write traning pattern2 failed\n");
581 edp_info->lt_info.lt_status = DP_LT_FAIL;
589 static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
592 unsigned int ret = EXYNOS_DP_SUCCESS;
593 unsigned char lane_stat, adj_req_sw, adj_req_em, i;
594 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
595 unsigned char interlane_aligned = 0;
597 unsigned char f_lane_cnt;
598 unsigned char sink_stat;
602 ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
603 if (ret != EXYNOS_DP_SUCCESS) {
604 printf("DP read lane status failed\n");
605 edp_info->lt_info.lt_status = DP_LT_FAIL;
609 debug("DP lane stat : %x\n", lane_stat);
611 if (lane_stat & DP_LANE_STAT_CR_DONE) {
612 ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
614 if (ret != EXYNOS_DP_SUCCESS) {
615 edp_info->lt_info.lt_status = DP_LT_FAIL;
620 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
622 for (i = 0; i < edp_info->lane_cnt; i++) {
623 ret = exynos_dp_read_dpcd_adj_req(i,
624 &adj_req_sw, &adj_req_em);
625 if (ret != EXYNOS_DP_SUCCESS) {
626 printf("DP read adj req 1 failed\n");
627 edp_info->lt_info.lt_status = DP_LT_FAIL;
633 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
635 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
636 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
637 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
638 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
642 if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
643 (lane_stat&DP_LANE_STAT_SYM_LOCK))
644 && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
645 debug("DP Equalizer training succeed\n");
647 f_bw = exynos_dp_get_link_bandwidth();
648 f_lane_cnt = exynos_dp_get_lane_count();
650 debug("DP final BandWidth : %x\n", f_bw);
651 debug("DP final Lane Count : %x\n", f_lane_cnt);
653 edp_info->lt_info.lt_status = DP_LT_FINISHED;
655 exynos_dp_equalizer_err_link(edp_info);
658 edp_info->lt_info.ep_loop++;
660 if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
661 if (edp_info->lane_bw == DP_LANE_BW_2_70) {
662 ret = exynos_dp_reduce_link_rate(
665 edp_info->lt_info.lt_status =
667 exynos_dp_equalizer_err_link(edp_info);
670 for (i = 0; i < edp_info->lane_cnt; i++)
671 exynos_dp_set_lanex_pre_emphasis(
674 ret = exynos_dp_write_bytes_to_dpcd(
675 DPCD_TRAINING_LANE0_SET,
677 if (ret != EXYNOS_DP_SUCCESS) {
678 printf("DP set lt pattern failed\n");
679 edp_info->lt_info.lt_status =
681 exynos_dp_equalizer_err_link(edp_info);
685 } else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
686 ret = exynos_dp_reduce_link_rate(edp_info);
688 edp_info->lt_info.lt_status = DP_LT_FAIL;
689 exynos_dp_equalizer_err_link(edp_info);
695 static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
697 unsigned int ret = 0;
698 int training_finished;
700 /* Turn off unnecessary lane */
701 if (edp_info->lane_cnt == 1)
702 exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
704 training_finished = 0;
706 edp_info->lt_info.lt_status = DP_LT_START;
709 while (!training_finished) {
710 switch (edp_info->lt_info.lt_status) {
712 ret = exynos_dp_link_start(edp_info);
713 if (ret != EXYNOS_DP_SUCCESS) {
714 printf("DP LT:link start failed\n");
719 ret = exynos_dp_process_clock_recovery(edp_info);
720 if (ret != EXYNOS_DP_SUCCESS) {
721 printf("DP LT:clock recovery failed\n");
726 ret = exynos_dp_process_equalizer_training(edp_info);
727 if (ret != EXYNOS_DP_SUCCESS) {
728 printf("DP LT:equalizer training failed\n");
733 training_finished = 1;
743 static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
747 exynos_dp_init_training();
749 ret = exynos_dp_sw_link_training(edp_info);
750 if (ret != EXYNOS_DP_SUCCESS)
751 printf("DP dp_sw_link_traning() failed\n");
756 static void exynos_dp_enable_scramble(unsigned int enable)
761 exynos_dp_enable_scrambling(DP_ENABLE);
763 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
765 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
766 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
768 exynos_dp_enable_scrambling(DP_DISABLE);
769 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
771 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
772 (u8)(data | DPCD_SCRAMBLING_DISABLED));
776 static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
778 unsigned int ret = 0;
779 unsigned int retry_cnt;
783 if (edp_info->video_info.master_mode) {
784 printf("DP does not support master mode\n");
788 exynos_dp_config_video_slave_mode(&edp_info->video_info);
791 exynos_dp_set_video_color_format(&edp_info->video_info);
793 if (edp_info->video_info.bist_mode) {
794 if (exynos_dp_config_video_bist(edp_info) != 0)
798 ret = exynos_dp_get_pll_lock_status();
799 if (ret != PLL_LOCKED) {
800 printf("DP PLL is not locked yet\n");
804 if (edp_info->video_info.master_mode == 0) {
807 ret = exynos_dp_is_slave_video_stream_clock_on();
808 if (ret != EXYNOS_DP_SUCCESS) {
809 if (retry_cnt == 0) {
810 printf("DP stream_clock_on failed\n");
820 /* Set to use the register calculated M/N video */
821 exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
823 /* For video bist, Video timing must be generated by register */
824 exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
826 /* Enable video bist */
827 if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
828 edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
829 edp_info->video_info.bist_pattern != COLOR_SQUARE)
830 exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
832 exynos_dp_enable_video_bist(DP_DISABLE);
834 /* Disable video mute */
835 exynos_dp_enable_video_mute(DP_DISABLE);
837 /* Configure video Master or Slave mode */
838 exynos_dp_enable_video_master(edp_info->video_info.master_mode);
841 exynos_dp_start_video();
843 if (edp_info->video_info.master_mode == 0) {
846 ret = exynos_dp_is_video_stream_on();
847 if (ret != EXYNOS_DP_SUCCESS) {
848 if (retry_cnt == 0) {
849 printf("DP Timeout of video stream\n");
862 unsigned int exynos_init_dp(void)
865 struct edp_device_info *edp_info;
867 edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
869 debug("failed to allocate edp device object.\n");
873 edp_info = dp_pd->edp_dev_info;
874 if (edp_info == NULL) {
875 debug("failed to get edp_info data.\n");
879 exynos_dp_disp_info(&edp_info->disp_info);
881 exynos_set_dp_phy(1);
883 ret = exynos_dp_init_dp();
884 if (ret != EXYNOS_DP_SUCCESS) {
885 printf("DP exynos_dp_init_dp() failed\n");
889 ret = exynos_dp_handle_edid(edp_info);
890 if (ret != EXYNOS_DP_SUCCESS) {
891 printf("EDP handle_edid fail\n");
895 ret = exynos_dp_set_link_train(edp_info);
896 if (ret != EXYNOS_DP_SUCCESS) {
897 printf("DP link training fail\n");
901 exynos_dp_enable_scramble(DP_ENABLE);
902 exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
903 exynos_dp_enable_enhanced_mode(DP_ENABLE);
905 exynos_dp_set_link_bandwidth(edp_info->lane_bw);
906 exynos_dp_set_lane_count(edp_info->lane_cnt);
908 exynos_dp_init_video();
909 ret = exynos_dp_config_video(edp_info);
910 if (ret != EXYNOS_DP_SUCCESS) {
911 printf("Exynos DP init failed\n");
915 printf("Exynos DP init done\n");
920 void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd)
923 debug("pd is NULL\n");