5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
7 * Linux IPU driver for MX51:
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/types.h>
17 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/arch/sys_proto.h>
27 extern struct mxc_ccm_reg *mxc_ccm;
28 extern u32 *ipu_cpmem_base;
30 struct ipu_ch_param_word {
36 struct ipu_ch_param_word word[2];
39 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
41 #define _param_word(base, w) \
42 (((struct ipu_ch_param *)(base))->word[(w)].data)
44 #define ipu_ch_param_set_field(base, w, bit, size, v) { \
46 int off = (bit) % 32; \
47 _param_word(base, w)[i] |= (v) << off; \
48 if (((bit) + (size) - 1) / 32 > i) { \
49 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
53 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \
55 int off = (bit) % 32; \
56 u32 mask = (1UL << size) - 1; \
57 u32 temp = _param_word(base, w)[i]; \
58 temp &= ~(mask << off); \
59 _param_word(base, w)[i] = temp | (v) << off; \
60 if (((bit) + (size) - 1) / 32 > i) { \
61 temp = _param_word(base, w)[i + 1]; \
62 temp &= ~(mask >> (32 - off)); \
63 _param_word(base, w)[i + 1] = \
64 temp | ((v) >> (off ? (32 - off) : 0)); \
68 #define ipu_ch_param_read_field(base, w, bit, size) ({ \
71 int off = (bit) % 32; \
72 u32 mask = (1UL << size) - 1; \
73 u32 temp1 = _param_word(base, w)[i]; \
74 temp1 = mask & (temp1 >> off); \
75 if (((bit)+(size) - 1) / 32 > i) { \
76 temp2 = _param_word(base, w)[i + 1]; \
77 temp2 &= mask >> (off ? (32 - off) : 0); \
78 temp1 |= temp2 << (off ? (32 - off) : 0); \
83 #define IPU_SW_RST_TOUT_USEC (10000)
85 #define IPUV3_CLK_MX51 133000000
86 #define IPUV3_CLK_MX53 200000000
87 #define IPUV3_CLK_MX6Q 264000000
88 #define IPUV3_CLK_MX6DL 198000000
90 void clk_enable(struct clk *clk)
93 if (clk->usecount++ == 0) {
99 void clk_disable(struct clk *clk)
102 if (!(--clk->usecount)) {
109 int clk_get_usecount(struct clk *clk)
114 return clk->usecount;
117 u32 clk_get_rate(struct clk *clk)
125 struct clk *clk_get_parent(struct clk *clk)
133 int clk_set_rate(struct clk *clk, unsigned long rate)
139 clk->set_rate(clk, rate);
144 long clk_round_rate(struct clk *clk, unsigned long rate)
146 if (clk == NULL || !clk->round_rate)
149 return clk->round_rate(clk, rate);
152 int clk_set_parent(struct clk *clk, struct clk *parent)
154 clk->parent = parent;
156 return clk->set_parent(clk, parent);
160 static int clk_ipu_enable(struct clk *clk)
164 reg = __raw_readl(clk->enable_reg);
165 reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
166 __raw_writel(reg, clk->enable_reg);
168 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
169 /* Handshake with IPU when certain clock rates are changed. */
170 reg = __raw_readl(&mxc_ccm->ccdr);
171 reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
172 __raw_writel(reg, &mxc_ccm->ccdr);
174 /* Handshake with IPU when LPM is entered as its enabled. */
175 reg = __raw_readl(&mxc_ccm->clpcr);
176 reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
177 __raw_writel(reg, &mxc_ccm->clpcr);
182 static void clk_ipu_disable(struct clk *clk)
186 reg = __raw_readl(clk->enable_reg);
187 reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
188 __raw_writel(reg, clk->enable_reg);
190 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
192 * No handshake with IPU whe dividers are changed
193 * as its not enabled.
195 reg = __raw_readl(&mxc_ccm->ccdr);
196 reg |= MXC_CCM_CCDR_IPU_HS_MASK;
197 __raw_writel(reg, &mxc_ccm->ccdr);
199 /* No handshake with IPU when LPM is entered as its not enabled. */
200 reg = __raw_readl(&mxc_ccm->clpcr);
201 reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
202 __raw_writel(reg, &mxc_ccm->clpcr);
207 static struct clk ipu_clk = {
209 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
210 .enable_reg = (u32 *)(CCM_BASE_ADDR +
211 offsetof(struct mxc_ccm_reg, CCGR5)),
212 .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
214 .enable_reg = (u32 *)(CCM_BASE_ADDR +
215 offsetof(struct mxc_ccm_reg, CCGR3)),
216 .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
218 .enable = clk_ipu_enable,
219 .disable = clk_ipu_disable,
223 #if !defined CONFIG_SYS_LDB_CLOCK
224 #define CONFIG_SYS_LDB_CLOCK 65000000
227 static struct clk ldb_clk = {
229 .rate = CONFIG_SYS_LDB_CLOCK,
234 struct clk *g_ipu_clk;
235 struct clk *g_ldb_clk;
236 unsigned char g_ipu_clk_enabled;
237 struct clk *g_di_clk[2];
238 struct clk *g_pixel_clk[2];
239 unsigned char g_dc_di_assignment[10];
240 uint32_t g_channel_init_mask;
241 uint32_t g_channel_enable_mask;
243 static int ipu_dc_use_count;
244 static int ipu_dp_use_count;
245 static int ipu_dmfc_use_count;
246 static int ipu_di_use_count[2];
249 u32 *ipu_dc_tmpl_reg;
251 /* Static functions */
253 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
255 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
258 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
260 return ((uint32_t) ch >> (6 * type)) & 0x3F;
263 /* Either DP BG or DP FG can be graphic window */
264 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
266 return (dma_chan == 23 || dma_chan == 27);
269 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
271 return ((dma_chan >= 23) && (dma_chan <= 29));
275 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
278 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
282 #define idma_is_valid(ch) (ch != NO_DMA)
283 #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
284 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
286 static void ipu_pixel_clk_recalc(struct clk *clk)
289 u64 final_rate = (unsigned long long)clk->parent->rate * 16;
291 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
292 debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
293 div, final_rate, clk->parent->rate);
297 do_div(final_rate, div);
298 clk->rate = final_rate;
302 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
307 u64 parent_rate = (unsigned long long)clk->parent->rate * 16;
311 * Fractional part is 4 bits,
312 * so simply multiply by 2^4 to get fractional part.
315 remainder = do_div(div, rate);
316 /* Round the divider value */
317 if (remainder > (rate / 2))
319 if (div < 0x10) /* Min DI disp clock divider is 1 */
324 /* Round up divider if it gets us closer to desired pix clk */
325 if ((div & 0xC) == 0xC) {
330 final_rate = parent_rate;
331 do_div(final_rate, div);
336 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
338 u64 div, parent_rate;
341 parent_rate = (unsigned long long)clk->parent->rate * 16;
343 remainder = do_div(div, rate);
344 /* Round the divider value */
345 if (remainder > (rate / 2))
348 /* Round up divider if it gets us closer to desired pix clk */
349 if ((div & 0xC) == 0xC) {
354 debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div);
356 __raw_writel(div, DI_BS_CLKGEN0(clk->id));
359 * Setup pixel clock timing
360 * Down time is half of period
362 __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
364 do_div(parent_rate, div);
366 clk->rate = parent_rate;
371 static int ipu_pixel_clk_enable(struct clk *clk)
373 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
374 disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
375 __raw_writel(disp_gen, IPU_DISP_GEN);
380 static void ipu_pixel_clk_disable(struct clk *clk)
382 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
383 disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
384 __raw_writel(disp_gen, IPU_DISP_GEN);
388 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
390 u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
392 if (parent == g_ipu_clk)
393 di_gen &= ~DI_GEN_DI_CLK_EXT;
394 else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
395 di_gen |= DI_GEN_DI_CLK_EXT;
399 __raw_writel(di_gen, DI_GENERAL(clk->id));
400 ipu_pixel_clk_recalc(clk);
404 static struct clk pixel_clk[] = {
408 .recalc = ipu_pixel_clk_recalc,
409 .set_rate = ipu_pixel_clk_set_rate,
410 .round_rate = ipu_pixel_clk_round_rate,
411 .set_parent = ipu_pixel_clk_set_parent,
412 .enable = ipu_pixel_clk_enable,
413 .disable = ipu_pixel_clk_disable,
419 .recalc = ipu_pixel_clk_recalc,
420 .set_rate = ipu_pixel_clk_set_rate,
421 .round_rate = ipu_pixel_clk_round_rate,
422 .set_parent = ipu_pixel_clk_set_parent,
423 .enable = ipu_pixel_clk_enable,
424 .disable = ipu_pixel_clk_disable,
430 * This function resets IPU
432 static void ipu_reset(void)
436 int timeout = IPU_SW_RST_TOUT_USEC;
438 reg = (u32 *)SRC_BASE_ADDR;
439 value = __raw_readl(reg);
440 value = value | SW_IPU_RST;
441 __raw_writel(value, reg);
443 while (__raw_readl(reg) & SW_IPU_RST) {
446 printf("ipu software reset timeout\n");
453 * This function is called by the driver framework to initialize the IPU
456 * @param dev The device structure for the IPU passed in by the
459 * @return Returns 0 on success or negative error code on error
463 unsigned long ipu_base;
464 #if defined CONFIG_MX51
467 u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
468 u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
470 __raw_writel(0xF00, reg_hsc_mcd);
472 /* CSI mode reserved*/
473 temp = __raw_readl(reg_hsc_mxt_conf);
474 __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
476 temp = __raw_readl(reg_hsc_mxt_conf);
477 __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
480 ipu_base = IPU_CTRL_BASE_ADDR;
481 ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
482 ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
484 g_pixel_clk[0] = &pixel_clk[0];
485 g_pixel_clk[1] = &pixel_clk[1];
487 g_ipu_clk = &ipu_clk;
488 #if defined(CONFIG_MX51)
489 g_ipu_clk->rate = IPUV3_CLK_MX51;
490 #elif defined(CONFIG_MX53)
491 g_ipu_clk->rate = IPUV3_CLK_MX53;
493 g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;
495 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
496 g_ldb_clk = &ldb_clk;
497 debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
500 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
501 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
502 clk_enable(g_ipu_clk);
507 __raw_writel(0x807FFFFF, IPU_MEM_RST);
508 while (__raw_readl(IPU_MEM_RST) & 0x80000000)
511 ipu_init_dc_mappings();
513 __raw_writel(0, IPU_INT_CTRL(5));
514 __raw_writel(0, IPU_INT_CTRL(6));
515 __raw_writel(0, IPU_INT_CTRL(9));
516 __raw_writel(0, IPU_INT_CTRL(10));
519 ipu_dmfc_init(DMFC_NORMAL, 1);
521 /* Set sync refresh channels as high priority */
522 __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
524 /* Set MCU_T to divide MCU access window into 2 */
525 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
527 clk_disable(g_ipu_clk);
532 void ipu_dump_registers(void)
534 debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
535 debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
536 debug("IDMAC_CHA_EN1 = \t0x%08X\n",
537 __raw_readl(IDMAC_CHA_EN(0)));
538 debug("IDMAC_CHA_EN2 = \t0x%08X\n",
539 __raw_readl(IDMAC_CHA_EN(32)));
540 debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
541 __raw_readl(IDMAC_CHA_PRI(0)));
542 debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
543 __raw_readl(IDMAC_CHA_PRI(32)));
544 debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
545 __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
546 debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
547 __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
548 debug("DMFC_WR_CHAN = \t0x%08X\n",
549 __raw_readl(DMFC_WR_CHAN));
550 debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
551 __raw_readl(DMFC_WR_CHAN_DEF));
552 debug("DMFC_DP_CHAN = \t0x%08X\n",
553 __raw_readl(DMFC_DP_CHAN));
554 debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
555 __raw_readl(DMFC_DP_CHAN_DEF));
556 debug("DMFC_IC_CTRL = \t0x%08X\n",
557 __raw_readl(DMFC_IC_CTRL));
558 debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
559 __raw_readl(IPU_FS_PROC_FLOW1));
560 debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
561 __raw_readl(IPU_FS_PROC_FLOW2));
562 debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
563 __raw_readl(IPU_FS_PROC_FLOW3));
564 debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
565 __raw_readl(IPU_FS_DISP_FLOW1));
569 * This function is called to initialize a logical IPU channel.
571 * @param channel Input parameter for the logical channel ID to init.
573 * @param params Input parameter containing union of channel
574 * initialization parameters.
576 * @return Returns 0 on success or negative error code on fail
578 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
583 debug("init channel = %d\n", IPU_CHAN_ID(channel));
585 if (g_ipu_clk_enabled == 0) {
586 g_ipu_clk_enabled = 1;
587 clk_enable(g_ipu_clk);
591 if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
592 printf("Warning: channel already initialized %d\n",
593 IPU_CHAN_ID(channel));
596 ipu_conf = __raw_readl(IPU_CONF);
600 if (params->mem_dc_sync.di > 1) {
605 g_dc_di_assignment[1] = params->mem_dc_sync.di;
606 ipu_dc_init(1, params->mem_dc_sync.di,
607 params->mem_dc_sync.interlaced);
608 ipu_di_use_count[params->mem_dc_sync.di]++;
610 ipu_dmfc_use_count++;
613 if (params->mem_dp_bg_sync.di > 1) {
618 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
619 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
620 params->mem_dp_bg_sync.out_pixel_fmt);
621 ipu_dc_init(5, params->mem_dp_bg_sync.di,
622 params->mem_dp_bg_sync.interlaced);
623 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
626 ipu_dmfc_use_count++;
629 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
630 params->mem_dp_fg_sync.out_pixel_fmt);
634 ipu_dmfc_use_count++;
637 printf("Missing channel initialization\n");
641 /* Enable IPU sub module */
642 g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
643 if (ipu_dc_use_count == 1)
644 ipu_conf |= IPU_CONF_DC_EN;
645 if (ipu_dp_use_count == 1)
646 ipu_conf |= IPU_CONF_DP_EN;
647 if (ipu_dmfc_use_count == 1)
648 ipu_conf |= IPU_CONF_DMFC_EN;
649 if (ipu_di_use_count[0] == 1) {
650 ipu_conf |= IPU_CONF_DI0_EN;
652 if (ipu_di_use_count[1] == 1) {
653 ipu_conf |= IPU_CONF_DI1_EN;
656 __raw_writel(ipu_conf, IPU_CONF);
663 * This function is called to uninitialize a logical IPU channel.
665 * @param channel Input parameter for the logical channel ID to uninit.
667 void ipu_uninit_channel(ipu_channel_t channel)
670 uint32_t in_dma, out_dma = 0;
673 if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
674 debug("Channel already uninitialized %d\n",
675 IPU_CHAN_ID(channel));
680 * Make sure channel is disabled
681 * Get input and output dma channels
683 in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
684 out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
686 if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
687 idma_is_set(IDMAC_CHA_EN, out_dma)) {
689 "Channel %d is not disabled, disable first\n",
690 IPU_CHAN_ID(channel));
694 ipu_conf = __raw_readl(IPU_CONF);
696 /* Reset the double buffer */
697 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
698 __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
699 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
700 __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
705 ipu_di_use_count[g_dc_di_assignment[1]]--;
707 ipu_dmfc_use_count--;
710 ipu_dp_uninit(channel);
712 ipu_di_use_count[g_dc_di_assignment[5]]--;
715 ipu_dmfc_use_count--;
718 ipu_dp_uninit(channel);
721 ipu_dmfc_use_count--;
727 g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
729 if (ipu_dc_use_count == 0)
730 ipu_conf &= ~IPU_CONF_DC_EN;
731 if (ipu_dp_use_count == 0)
732 ipu_conf &= ~IPU_CONF_DP_EN;
733 if (ipu_dmfc_use_count == 0)
734 ipu_conf &= ~IPU_CONF_DMFC_EN;
735 if (ipu_di_use_count[0] == 0) {
736 ipu_conf &= ~IPU_CONF_DI0_EN;
738 if (ipu_di_use_count[1] == 0) {
739 ipu_conf &= ~IPU_CONF_DI1_EN;
742 __raw_writel(ipu_conf, IPU_CONF);
745 clk_disable(g_ipu_clk);
746 g_ipu_clk_enabled = 0;
751 static inline void ipu_ch_param_dump(int ch)
754 struct ipu_ch_param *p = ipu_ch_param_addr(ch);
755 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
756 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
757 p->word[0].data[3], p->word[0].data[4]);
758 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
759 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
760 p->word[1].data[3], p->word[1].data[4]);
762 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
764 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
766 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
769 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
771 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
773 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
775 debug("Width0 %d+1, ",
776 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
777 debug("Width1 %d+1, ",
778 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
779 debug("Width2 %d+1, ",
780 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
781 debug("Width3 %d+1, ",
782 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
783 debug("Offset0 %d, ",
784 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
785 debug("Offset1 %d, ",
786 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
787 debug("Offset2 %d, ",
788 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
789 debug("Offset3 %d\n",
790 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
794 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
795 int red_width, int red_offset,
796 int green_width, int green_offset,
797 int blue_width, int blue_offset,
798 int alpha_width, int alpha_offset)
800 /* Setup red width and offset */
801 ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
802 ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
803 /* Setup green width and offset */
804 ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
805 ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
806 /* Setup blue width and offset */
807 ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
808 ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
809 /* Setup alpha width and offset */
810 ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
811 ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
814 static void ipu_ch_param_init(int ch,
815 uint32_t pixel_fmt, uint32_t width,
816 uint32_t height, uint32_t stride,
817 uint32_t u, uint32_t v,
818 uint32_t uv_stride, dma_addr_t addr0,
821 uint32_t u_offset = 0;
822 uint32_t v_offset = 0;
823 struct ipu_ch_param params;
825 memset(¶ms, 0, sizeof(params));
827 ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1);
829 if ((ch == 8) || (ch == 9) || (ch == 10)) {
830 ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1);
831 ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1);
833 ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1);
834 ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1);
837 ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3);
838 ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3);
841 case IPU_PIX_FMT_GENERIC:
842 /*Represents 8-bit Generic data */
843 ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */
844 ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */
845 ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */
848 case IPU_PIX_FMT_GENERIC_32:
849 /*Represents 32-bit Generic data */
851 case IPU_PIX_FMT_RGB565:
852 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
853 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
854 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
856 ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16);
858 case IPU_PIX_FMT_BGR24:
859 ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
860 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
861 ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
863 ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
865 case IPU_PIX_FMT_RGB24:
866 case IPU_PIX_FMT_YUV444:
867 ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
868 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
869 ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
871 ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24);
873 case IPU_PIX_FMT_BGRA32:
874 case IPU_PIX_FMT_BGR32:
875 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
876 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
877 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
879 ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0);
881 case IPU_PIX_FMT_RGBA32:
882 case IPU_PIX_FMT_RGB32:
883 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
884 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
885 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
887 ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0);
889 case IPU_PIX_FMT_ABGR32:
890 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
891 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
893 ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
895 case IPU_PIX_FMT_UYVY:
896 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
897 ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */
898 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
900 case IPU_PIX_FMT_YUYV:
901 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
902 ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */
903 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
905 case IPU_PIX_FMT_YUV420P2:
906 case IPU_PIX_FMT_YUV420P:
907 ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */
909 if (uv_stride < stride / 2)
910 uv_stride = stride / 2;
912 u_offset = stride * height;
913 v_offset = u_offset + (uv_stride * height / 2);
915 if ((ch == 8) || (ch == 9) || (ch == 10)) {
916 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15);
917 uv_stride = uv_stride*2;
919 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31);
922 case IPU_PIX_FMT_YVU422P:
923 /* BPP & pixel format */
924 ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
925 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
927 if (uv_stride < stride / 2)
928 uv_stride = stride / 2;
930 v_offset = (v == 0) ? stride * height : v;
931 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
933 case IPU_PIX_FMT_YUV422P:
934 /* BPP & pixel format */
935 ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
936 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
938 if (uv_stride < stride / 2)
939 uv_stride = stride / 2;
941 u_offset = (u == 0) ? stride * height : u;
942 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
944 case IPU_PIX_FMT_NV12:
945 /* BPP & pixel format */
946 ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */
947 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
949 u_offset = (u == 0) ? stride * height : u;
952 puts("mxc ipu: unimplemented pixel format\n");
958 ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1);
960 /* Get the uv offset from user when need cropping */
966 /* UBO and VBO are 22-bit */
967 if (u_offset/8 > 0x3fffff)
968 puts("The value of U offset exceeds IPU limitation\n");
969 if (v_offset/8 > 0x3fffff)
970 puts("The value of V offset exceeds IPU limitation\n");
972 ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8);
973 ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8);
975 debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
976 memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params));
980 * This function is called to initialize a buffer for logical IPU channel.
982 * @param channel Input parameter for the logical channel ID.
984 * @param type Input parameter which buffer to initialize.
986 * @param pixel_fmt Input parameter for pixel format of buffer.
987 * Pixel format is a FOURCC ASCII code.
989 * @param width Input parameter for width of buffer in pixels.
991 * @param height Input parameter for height of buffer in pixels.
993 * @param stride Input parameter for stride length of buffer
996 * @param phyaddr_0 Input parameter buffer 0 physical address.
998 * @param phyaddr_1 Input parameter buffer 1 physical address.
999 * Setting this to a value other than NULL enables
1000 * double buffering mode.
1002 * @param u private u offset for additional cropping,
1005 * @param v private v offset for additional cropping,
1008 * @return Returns 0 on success or negative error code on fail
1010 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
1012 uint16_t width, uint16_t height,
1014 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
1015 uint32_t u, uint32_t v)
1020 dma_chan = channel_2_dma(channel, type);
1021 if (!idma_is_valid(dma_chan))
1024 if (stride < width * bytes_per_pixel(pixel_fmt))
1025 stride = width * bytes_per_pixel(pixel_fmt);
1029 "Stride not 32-bit aligned, stride = %d\n", stride);
1032 /* Build parameter memory data for DMA channel */
1033 ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
1034 phyaddr_0, phyaddr_1);
1036 if (ipu_is_dmfc_chan(dma_chan)) {
1037 ipu_dmfc_set_wait4eot(dma_chan, width);
1040 if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
1041 ipu_ch_param_set_high_priority(dma_chan);
1043 ipu_ch_param_dump(dma_chan);
1045 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
1047 reg |= idma_mask(dma_chan);
1049 reg &= ~idma_mask(dma_chan);
1050 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1052 /* Reset to buffer 0 */
1053 __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
1059 * This function enables a logical channel.
1061 * @param channel Input parameter for the logical channel ID.
1063 * @return This function returns 0 on success or negative error code on
1066 int32_t ipu_enable_channel(ipu_channel_t channel)
1072 if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1073 printf("Warning: channel already enabled %d\n",
1074 IPU_CHAN_ID(channel));
1077 /* Get input and output dma channels */
1078 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1079 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1081 if (idma_is_valid(in_dma)) {
1082 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1083 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1085 if (idma_is_valid(out_dma)) {
1086 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1087 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1090 if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1091 (channel == MEM_FG_SYNC))
1092 ipu_dp_dc_enable(channel);
1094 g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1100 * This function clear buffer ready for a logical channel.
1102 * @param channel Input parameter for the logical channel ID.
1104 * @param type Input parameter which buffer to clear.
1106 * @param bufNum Input parameter for which buffer number clear
1110 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1113 uint32_t dma_ch = channel_2_dma(channel, type);
1115 if (!idma_is_valid(dma_ch))
1118 __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1120 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1121 __raw_writel(idma_mask(dma_ch),
1122 IPU_CHA_BUF0_RDY(dma_ch));
1125 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1126 __raw_writel(idma_mask(dma_ch),
1127 IPU_CHA_BUF1_RDY(dma_ch));
1130 __raw_writel(0x0, IPU_GPR); /* write one to set */
1134 * This function disables a logical channel.
1136 * @param channel Input parameter for the logical channel ID.
1138 * @param wait_for_stop Flag to set whether to wait for channel end
1139 * of frame or return immediately.
1141 * @return This function returns 0 on success or negative error code on
1144 int32_t ipu_disable_channel(ipu_channel_t channel)
1150 if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1151 debug("Channel already disabled %d\n",
1152 IPU_CHAN_ID(channel));
1156 /* Get input and output dma channels */
1157 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1158 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1160 if ((idma_is_valid(in_dma) &&
1161 !idma_is_set(IDMAC_CHA_EN, in_dma))
1162 && (idma_is_valid(out_dma) &&
1163 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1166 if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1167 (channel == MEM_DC_SYNC)) {
1168 ipu_dp_dc_disable(channel, 0);
1171 /* Disable DMA channel(s) */
1172 if (idma_is_valid(in_dma)) {
1173 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1174 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1175 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1177 if (idma_is_valid(out_dma)) {
1178 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1179 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1180 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1183 g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1185 /* Set channel buffers NOT to be ready */
1186 if (idma_is_valid(in_dma)) {
1187 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1188 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1190 if (idma_is_valid(out_dma)) {
1191 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1192 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1198 uint32_t bytes_per_pixel(uint32_t fmt)
1201 case IPU_PIX_FMT_GENERIC: /*generic data */
1202 case IPU_PIX_FMT_RGB332:
1203 case IPU_PIX_FMT_YUV420P:
1204 case IPU_PIX_FMT_YUV422P:
1207 case IPU_PIX_FMT_RGB565:
1208 case IPU_PIX_FMT_YUYV:
1209 case IPU_PIX_FMT_UYVY:
1212 case IPU_PIX_FMT_BGR24:
1213 case IPU_PIX_FMT_RGB24:
1216 case IPU_PIX_FMT_GENERIC_32: /*generic data */
1217 case IPU_PIX_FMT_BGR32:
1218 case IPU_PIX_FMT_BGRA32:
1219 case IPU_PIX_FMT_RGB32:
1220 case IPU_PIX_FMT_RGBA32:
1221 case IPU_PIX_FMT_ABGR32:
1231 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1234 case IPU_PIX_FMT_RGB666:
1235 case IPU_PIX_FMT_RGB565:
1236 case IPU_PIX_FMT_BGR24:
1237 case IPU_PIX_FMT_RGB24:
1238 case IPU_PIX_FMT_BGR32:
1239 case IPU_PIX_FMT_BGRA32:
1240 case IPU_PIX_FMT_RGB32:
1241 case IPU_PIX_FMT_RGBA32:
1242 case IPU_PIX_FMT_ABGR32:
1243 case IPU_PIX_FMT_LVDS666:
1244 case IPU_PIX_FMT_LVDS888:
1255 /* should be removed when clk framework is availiable */
1256 int ipu_set_ldb_clock(int rate)
1258 ldb_clk.rate = rate;
1263 bool ipu_clk_enabled(void)
1265 return g_ipu_clk_enabled;