2 * Copyright (C) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
14 #include <asm/intel_regs.h>
18 #include <asm/arch/pch.h>
19 #include <asm/arch/sandybridge.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 struct gt_powermeter {
28 /* These are magic values - unfortunately the meaning is unknown */
29 static const struct gt_powermeter snb_pm_gt1[] = {
30 { 0xa200, 0xcc000000 },
31 { 0xa204, 0x07000040 },
32 { 0xa208, 0x0000fe00 },
33 { 0xa20c, 0x00000000 },
34 { 0xa210, 0x17000000 },
35 { 0xa214, 0x00000021 },
36 { 0xa218, 0x0817fe19 },
37 { 0xa21c, 0x00000000 },
38 { 0xa220, 0x00000000 },
39 { 0xa224, 0xcc000000 },
40 { 0xa228, 0x07000040 },
41 { 0xa22c, 0x0000fe00 },
42 { 0xa230, 0x00000000 },
43 { 0xa234, 0x17000000 },
44 { 0xa238, 0x00000021 },
45 { 0xa23c, 0x0817fe19 },
46 { 0xa240, 0x00000000 },
47 { 0xa244, 0x00000000 },
48 { 0xa248, 0x8000421e },
52 static const struct gt_powermeter snb_pm_gt2[] = {
53 { 0xa200, 0x330000a6 },
54 { 0xa204, 0x402d0031 },
55 { 0xa208, 0x00165f83 },
56 { 0xa20c, 0xf1000000 },
57 { 0xa210, 0x00000000 },
58 { 0xa214, 0x00160016 },
59 { 0xa218, 0x002a002b },
60 { 0xa21c, 0x00000000 },
61 { 0xa220, 0x00000000 },
62 { 0xa224, 0x330000a6 },
63 { 0xa228, 0x402d0031 },
64 { 0xa22c, 0x00165f83 },
65 { 0xa230, 0xf1000000 },
66 { 0xa234, 0x00000000 },
67 { 0xa238, 0x00160016 },
68 { 0xa23c, 0x002a002b },
69 { 0xa240, 0x00000000 },
70 { 0xa244, 0x00000000 },
71 { 0xa248, 0x8000421e },
75 static const struct gt_powermeter ivb_pm_gt1[] = {
76 { 0xa800, 0x00000000 },
77 { 0xa804, 0x00021c00 },
78 { 0xa808, 0x00000403 },
79 { 0xa80c, 0x02001700 },
80 { 0xa810, 0x05000200 },
81 { 0xa814, 0x00000000 },
82 { 0xa818, 0x00690500 },
83 { 0xa81c, 0x0000007f },
84 { 0xa820, 0x01002501 },
85 { 0xa824, 0x00000300 },
86 { 0xa828, 0x01000331 },
87 { 0xa82c, 0x0000000c },
88 { 0xa830, 0x00010016 },
89 { 0xa834, 0x01100101 },
90 { 0xa838, 0x00010103 },
91 { 0xa83c, 0x00041300 },
92 { 0xa840, 0x00000b30 },
93 { 0xa844, 0x00000000 },
94 { 0xa848, 0x7f000000 },
95 { 0xa84c, 0x05000008 },
96 { 0xa850, 0x00000001 },
97 { 0xa854, 0x00000004 },
98 { 0xa858, 0x00000007 },
99 { 0xa85c, 0x00000000 },
100 { 0xa860, 0x00010000 },
101 { 0xa248, 0x0000221e },
102 { 0xa900, 0x00000000 },
103 { 0xa904, 0x00001c00 },
104 { 0xa908, 0x00000000 },
105 { 0xa90c, 0x06000000 },
106 { 0xa910, 0x09000200 },
107 { 0xa914, 0x00000000 },
108 { 0xa918, 0x00590000 },
109 { 0xa91c, 0x00000000 },
110 { 0xa920, 0x04002501 },
111 { 0xa924, 0x00000100 },
112 { 0xa928, 0x03000410 },
113 { 0xa92c, 0x00000000 },
114 { 0xa930, 0x00020000 },
115 { 0xa934, 0x02070106 },
116 { 0xa938, 0x00010100 },
117 { 0xa93c, 0x00401c00 },
118 { 0xa940, 0x00000000 },
119 { 0xa944, 0x00000000 },
120 { 0xa948, 0x10000e00 },
121 { 0xa94c, 0x02000004 },
122 { 0xa950, 0x00000001 },
123 { 0xa954, 0x00000004 },
124 { 0xa960, 0x00060000 },
125 { 0xaa3c, 0x00001c00 },
126 { 0xaa54, 0x00000004 },
127 { 0xaa60, 0x00060000 },
131 static const struct gt_powermeter ivb_pm_gt2_17w[] = {
132 { 0xa800, 0x20000000 },
133 { 0xa804, 0x000e3800 },
134 { 0xa808, 0x00000806 },
135 { 0xa80c, 0x0c002f00 },
136 { 0xa810, 0x0c000800 },
137 { 0xa814, 0x00000000 },
138 { 0xa818, 0x00d20d00 },
139 { 0xa81c, 0x000000ff },
140 { 0xa820, 0x03004b02 },
141 { 0xa824, 0x00000600 },
142 { 0xa828, 0x07000773 },
143 { 0xa82c, 0x00000000 },
144 { 0xa830, 0x00020032 },
145 { 0xa834, 0x1520040d },
146 { 0xa838, 0x00020105 },
147 { 0xa83c, 0x00083700 },
148 { 0xa840, 0x000016ff },
149 { 0xa844, 0x00000000 },
150 { 0xa848, 0xff000000 },
151 { 0xa84c, 0x0a000010 },
152 { 0xa850, 0x00000002 },
153 { 0xa854, 0x00000008 },
154 { 0xa858, 0x0000000f },
155 { 0xa85c, 0x00000000 },
156 { 0xa860, 0x00020000 },
157 { 0xa248, 0x0000221e },
158 { 0xa900, 0x00000000 },
159 { 0xa904, 0x00003800 },
160 { 0xa908, 0x00000000 },
161 { 0xa90c, 0x0c000000 },
162 { 0xa910, 0x12000800 },
163 { 0xa914, 0x00000000 },
164 { 0xa918, 0x00b20000 },
165 { 0xa91c, 0x00000000 },
166 { 0xa920, 0x08004b02 },
167 { 0xa924, 0x00000300 },
168 { 0xa928, 0x01000820 },
169 { 0xa92c, 0x00000000 },
170 { 0xa930, 0x00030000 },
171 { 0xa934, 0x15150406 },
172 { 0xa938, 0x00020300 },
173 { 0xa93c, 0x00903900 },
174 { 0xa940, 0x00000000 },
175 { 0xa944, 0x00000000 },
176 { 0xa948, 0x20001b00 },
177 { 0xa94c, 0x0a000010 },
178 { 0xa950, 0x00000000 },
179 { 0xa954, 0x00000008 },
180 { 0xa960, 0x00110000 },
181 { 0xaa3c, 0x00003900 },
182 { 0xaa54, 0x00000008 },
183 { 0xaa60, 0x00110000 },
187 static const struct gt_powermeter ivb_pm_gt2_35w[] = {
188 { 0xa800, 0x00000000 },
189 { 0xa804, 0x00030400 },
190 { 0xa808, 0x00000806 },
191 { 0xa80c, 0x0c002f00 },
192 { 0xa810, 0x0c000300 },
193 { 0xa814, 0x00000000 },
194 { 0xa818, 0x00d20d00 },
195 { 0xa81c, 0x000000ff },
196 { 0xa820, 0x03004b02 },
197 { 0xa824, 0x00000600 },
198 { 0xa828, 0x07000773 },
199 { 0xa82c, 0x00000000 },
200 { 0xa830, 0x00020032 },
201 { 0xa834, 0x1520040d },
202 { 0xa838, 0x00020105 },
203 { 0xa83c, 0x00083700 },
204 { 0xa840, 0x000016ff },
205 { 0xa844, 0x00000000 },
206 { 0xa848, 0xff000000 },
207 { 0xa84c, 0x0a000010 },
208 { 0xa850, 0x00000001 },
209 { 0xa854, 0x00000008 },
210 { 0xa858, 0x00000008 },
211 { 0xa85c, 0x00000000 },
212 { 0xa860, 0x00020000 },
213 { 0xa248, 0x0000221e },
214 { 0xa900, 0x00000000 },
215 { 0xa904, 0x00003800 },
216 { 0xa908, 0x00000000 },
217 { 0xa90c, 0x0c000000 },
218 { 0xa910, 0x12000800 },
219 { 0xa914, 0x00000000 },
220 { 0xa918, 0x00b20000 },
221 { 0xa91c, 0x00000000 },
222 { 0xa920, 0x08004b02 },
223 { 0xa924, 0x00000300 },
224 { 0xa928, 0x01000820 },
225 { 0xa92c, 0x00000000 },
226 { 0xa930, 0x00030000 },
227 { 0xa934, 0x15150406 },
228 { 0xa938, 0x00020300 },
229 { 0xa93c, 0x00903900 },
230 { 0xa940, 0x00000000 },
231 { 0xa944, 0x00000000 },
232 { 0xa948, 0x20001b00 },
233 { 0xa94c, 0x0a000010 },
234 { 0xa950, 0x00000000 },
235 { 0xa954, 0x00000008 },
236 { 0xa960, 0x00110000 },
237 { 0xaa3c, 0x00003900 },
238 { 0xaa54, 0x00000008 },
239 { 0xaa60, 0x00110000 },
243 static inline u32 gtt_read(void *bar, u32 reg)
245 return readl(bar + reg);
248 static inline void gtt_write(void *bar, u32 reg, u32 data)
250 writel(data, bar + reg);
253 static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
255 for (; pm && pm->reg; pm++)
256 gtt_write(bar, pm->reg, pm->value);
259 #define GTT_RETRY 1000
260 static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
262 unsigned try = GTT_RETRY;
266 data = gtt_read(bar, reg);
267 if ((data & mask) == value)
272 printf("GT init timeout\n");
276 static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
280 debug("GT Power Management Init, silicon = %#x\n", rev);
282 if (rev < IVB_STEP_C0) {
283 /* 1: Enable force wake */
284 gtt_write(gtt_bar, 0xa18c, 0x00000001);
285 gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
287 gtt_write(gtt_bar, 0xa180, 1 << 5);
288 gtt_write(gtt_bar, 0xa188, 0xffff0001);
289 gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
292 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
293 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
294 reg32 = gtt_read(gtt_bar, 0x42004);
295 reg32 |= (1 << 14) | (1 << 15);
296 gtt_write(gtt_bar, 0x42004, reg32);
299 if (rev >= IVB_STEP_A0) {
300 /* Display Reset Acknowledge Settings */
301 reg32 = gtt_read(gtt_bar, 0x45010);
302 reg32 |= (1 << 1) | (1 << 0);
303 gtt_write(gtt_bar, 0x45010, reg32);
306 /* 2: Get GT SKU from GTT+0x911c[13] */
307 reg32 = gtt_read(gtt_bar, 0x911c);
308 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
309 if (reg32 & (1 << 13)) {
310 debug("SNB GT1 Power Meter Weights\n");
311 gtt_write_powermeter(gtt_bar, snb_pm_gt1);
313 debug("SNB GT2 Power Meter Weights\n");
314 gtt_write_powermeter(gtt_bar, snb_pm_gt2);
317 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
319 if (reg32 & (1 << 13)) {
321 debug("IVB GT1 Power Meter Weights\n");
322 gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
325 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
330 debug("IVB GT2 17W Power Meter Weights\n");
331 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
332 } else if ((tdp >= 25) && (tdp <= 35)) {
334 debug("IVB GT2 25W-35W Power Meter Weights\n");
335 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
338 debug("IVB GT2 35W Power Meter Weights\n");
339 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
344 /* 3: Gear ratio map */
345 gtt_write(gtt_bar, 0xa004, 0x00000010);
348 gtt_write(gtt_bar, 0xa000, 0x00070020);
350 /* 5: Dynamic EU trip control */
351 gtt_write(gtt_bar, 0xa080, 0x00000004);
354 reg32 = gtt_read(gtt_bar, 0xa180);
355 reg32 |= (1 << 26) | (1 << 31);
356 /* (bit 20=1 for SNB step D1+ / IVB A0+) */
357 if (rev >= SNB_STEP_D1)
359 gtt_write(gtt_bar, 0xa180, reg32);
361 /* 6a: for SnB step D2+ only */
362 if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
363 (rev >= SNB_STEP_D2)) {
364 reg32 = gtt_read(gtt_bar, 0x9400);
366 gtt_write(gtt_bar, 0x9400, reg32);
368 reg32 = gtt_read(gtt_bar, 0x941c);
371 gtt_write(gtt_bar, 0x941c, reg32);
372 gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
375 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
376 reg32 = gtt_read(gtt_bar, 0x907c);
378 gtt_write(gtt_bar, 0x907c, reg32);
380 /* 6b: Clocking reset controls */
381 gtt_write(gtt_bar, 0x9424, 0x00000001);
383 /* 6b: Clocking reset controls */
384 gtt_write(gtt_bar, 0x9424, 0x00000000);
388 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
389 gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
390 /* Mailbox Cmd for RC6 VID */
391 gtt_write(gtt_bar, 0x138124, 0x80000004);
392 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
393 gtt_write(gtt_bar, 0x138124, 0x8000000a);
394 gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
398 gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
399 gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
400 gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
401 gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
402 gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
403 gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
406 gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
407 gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
408 gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
411 gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
412 gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
413 gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
414 gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
415 gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
418 gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
419 gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
420 gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
421 gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
422 gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
423 gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
424 gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
426 /* 11a: Enable Render Standby (RC6) */
427 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
429 * IvyBridge should also support DeepRenderStandby.
431 * Unfortunately it does not work reliably on all SKUs so
432 * disable it here and it can be enabled by the kernel.
434 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
436 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
439 /* 12: Normal Frequency Request */
440 /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
441 reg32 = readl(MCHBAR_REG(0x5998));
445 gtt_write(gtt_bar, 0xa008, reg32);
448 gtt_write(gtt_bar, 0xa024, 0x00000592);
450 /* 14: Enable PM Interrupts */
451 gtt_write(gtt_bar, 0x4402c, 0x03000076);
453 /* Clear 0x6c024 [8:6] */
454 reg32 = gtt_read(gtt_bar, 0x6c024);
455 reg32 &= ~0x000001c0;
456 gtt_write(gtt_bar, 0x6c024, reg32);
461 static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
463 const void *blob = gd->fdt_blob;
464 int node = dev_of_offset(dev);
465 u32 reg32, cycle_delay;
467 debug("GT Power Management Init (post VBIOS)\n");
469 /* 15: Deassert Force Wake */
470 if (rev < IVB_STEP_C0) {
471 gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
472 gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
474 gtt_write(gtt_bar, 0xa188, 0x1fffe);
475 if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
476 gtt_write(gtt_bar, 0xa188,
477 gtt_read(gtt_bar, 0xa188) | 1);
481 /* 16: SW RC Control */
482 gtt_write(gtt_bar, 0xa094, 0x00060000);
484 /* Setup Digital Port Hotplug */
485 reg32 = gtt_read(gtt_bar, 0xc4030);
489 if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
490 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
493 reg32 = (dp_hotplug[0] & 0x7) << 2;
494 reg32 |= (dp_hotplug[0] & 0x7) << 10;
495 reg32 |= (dp_hotplug[0] & 0x7) << 18;
496 gtt_write(gtt_bar, 0xc4030, reg32);
499 /* Setup Panel Power On Delays */
500 reg32 = gtt_read(gtt_bar, 0xc7208);
502 reg32 = (unsigned)fdtdec_get_int(blob, node,
503 "panel-port-select", 0) << 30;
504 reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
506 reg32 |= fdtdec_get_int(blob, node,
507 "panel-power-backlight-on-delay", 0);
508 gtt_write(gtt_bar, 0xc7208, reg32);
511 /* Setup Panel Power Off Delays */
512 reg32 = gtt_read(gtt_bar, 0xc720c);
514 reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
516 reg32 |= fdtdec_get_int(blob, node,
517 "panel-power-backlight-off-delay", 0);
518 gtt_write(gtt_bar, 0xc720c, reg32);
521 /* Setup Panel Power Cycle Delay */
522 cycle_delay = fdtdec_get_int(blob, node,
523 "intel,panel-power-cycle-delay", 0);
525 reg32 = gtt_read(gtt_bar, 0xc7210);
527 reg32 |= cycle_delay;
528 gtt_write(gtt_bar, 0xc7210, reg32);
531 /* Enable Backlight if needed */
532 reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
534 gtt_write(gtt_bar, 0x48250, (1 << 31));
535 gtt_write(gtt_bar, 0x48254, reg32);
537 reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
539 gtt_write(gtt_bar, 0xc8250, (1 << 31));
540 gtt_write(gtt_bar, 0xc8254, reg32);
547 * Some vga option roms are used for several chipsets but they only have one
548 * PCI ID in their header. If we encounter such an option rom, we need to do
549 * the mapping ourselves.
552 uint32_t board_map_oprom_vendev(uint32_t vendev)
555 case 0x80860102: /* GT1 Desktop */
556 case 0x8086010a: /* GT1 Server */
557 case 0x80860112: /* GT2 Desktop */
558 case 0x80860116: /* GT2 Mobile */
559 case 0x80860122: /* GT2 Desktop >=1.3GHz */
560 case 0x80860126: /* GT2 Mobile >=1.3GHz */
561 case 0x80860156: /* IVB */
562 case 0x80860166: /* IVB */
563 return 0x80860106; /* GT1 Mobile */
569 static int int15_handler(void)
573 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
575 switch (M.x86.R_AX) {
578 * Set Panel Fitting Hook:
579 * bit 2 = Graphics Stretching
580 * bit 1 = Text Stretching
581 * bit 0 = Centering (do not set with bit1 or bit2)
582 * 0 = video bios default
585 M.x86.R_CL = 0x00; /* Use video bios default */
590 * Boot Display Device Hook:
601 M.x86.R_CX = 0x0000; /* Use video bios default */
606 * Hook to select active LFP configuration:
607 * 00h = No LVDS, VBIOS does not enable LVDS
608 * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
609 * 02h = SVDO-LVDS, LFP driven by SVDO decoder
610 * 03h = eDP, LFP Driven by Int-DisplayPort encoder
613 M.x86.R_CX = 0x0003; /* eDP */
617 switch (M.x86.R_CH) {
631 /* Get SG/Non-SG mode */
637 /* Interrupt was not handled */
638 debug("Unknown INT15 5f70 function: 0x%02x\n",
647 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
653 static void sandybridge_setup_graphics(struct udevice *dev,
654 struct udevice *video_dev)
660 dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16);
662 case 0x0102: /* GT1 Desktop */
663 case 0x0106: /* GT1 Mobile */
664 case 0x010a: /* GT1 Server */
665 case 0x0112: /* GT2 Desktop */
666 case 0x0116: /* GT2 Mobile */
667 case 0x0122: /* GT2 Desktop >=1.3GHz */
668 case 0x0126: /* GT2 Mobile >=1.3GHz */
669 case 0x0156: /* IvyBridge */
670 case 0x0166: /* IvyBridge */
673 debug("Graphics not supported by this CPU/chipset\n");
677 debug("Initialising Graphics\n");
679 /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
680 dm_pci_read_config16(dev, GGC, ®16);
683 /* Program GTT memory by setting GGC[9:8] = 2MB */
686 /* Enable VGA decode */
688 dm_pci_write_config16(dev, GGC, reg16);
690 /* Enable 256MB aperture */
691 dm_pci_read_config8(video_dev, MSAC, ®8);
694 dm_pci_write_config8(video_dev, MSAC, reg8);
696 /* Erratum workarounds */
697 reg32 = readl(MCHBAR_REG(0x5f00));
698 reg32 |= (1 << 9) | (1 << 10);
699 writel(reg32, MCHBAR_REG(0x5f00));
701 /* Enable SA Clock Gating */
702 reg32 = readl(MCHBAR_REG(0x5f00));
703 writel(reg32 | 1, MCHBAR_REG(0x5f00));
705 /* GPU RC6 workaround for sighting 366252 */
706 reg32 = readl(MCHBAR_REG(0x5d14));
708 writel(reg32, MCHBAR_REG(0x5d14));
711 reg32 = readl(MCHBAR_REG(0x6120));
713 writel(reg32, MCHBAR_REG(0x6120));
715 reg32 = readl(MCHBAR_REG(0x5418));
716 reg32 |= (1 << 4) | (1 << 5);
717 writel(reg32, MCHBAR_REG(0x5418));
720 static int gma_func0_init(struct udevice *dev)
722 struct udevice *nbridge;
729 /* Enable PCH Display Port */
730 writew(0x0010, RCB_REG(DISPBDF));
731 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
733 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
736 rev = bridge_silicon_revision(nbridge);
737 sandybridge_setup_graphics(nbridge, dev);
739 /* IGD needs to be Bus Master */
740 dm_pci_read_config32(dev, PCI_COMMAND, ®32);
741 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
742 dm_pci_write_config32(dev, PCI_COMMAND, reg32);
744 /* Use write-combining for the graphics memory, 256MB */
745 base = dm_pci_read_bar32(dev, 2);
746 mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
749 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
750 debug("GT bar %p\n", gtt_bar);
751 ret = gma_pm_init_pre_vbios(gtt_bar, rev);
758 static int bd82x6x_video_probe(struct udevice *dev)
763 rev = gma_func0_init(dev);
766 ret = vbe_setup_video(dev, int15_handler);
770 /* Post VBIOS init */
771 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
772 ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
779 static const struct udevice_id bd82x6x_video_ids[] = {
780 { .compatible = "intel,gma" },
784 U_BOOT_DRIVER(bd82x6x_video) = {
785 .name = "bd82x6x_video",
787 .of_match = bd82x6x_video_ids,
788 .probe = bd82x6x_video_probe,