2 * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
8 * This file is a driver for Parade dP<->LVDS bridges. The original submission
9 * is for the ps8625 chip.
18 * Initialization of the chip is a process of writing certaing values into
19 * certain registers over i2c bus. The chip in fact responds to a range of
20 * addresses on the i2c bus, so for each written value three parameters are
21 * required: i2c address, register address and the actual value.
23 * The base address is derived from the device tree, only address offset is
24 * stored in the table below.
27 * struct reg_data() - data for a parade register write
29 * @addr_off offset from the i2c base address for parade
30 * @reg_addr register address to write
31 * @value value to be written
39 #define END_OF_TABLE 0xff /* Ficticious offset */
41 static const struct reg_data parade_values[] = {
42 {0x02, 0xa1, 0x01}, /* HPD low */
45 * [1:0] SW output 1.2V voltage is lower to 96%
50 * [5:4] = b01 0.5%, b10 1%, b11 1.5%
53 {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
56 * [3:2] CDR tune wait cycle before
57 * measure for fine tune b00: 1us,
58 * 01: 0.5us, 10:2us, 11:4us.
61 {0x04, 0x89, 0x08}, /* [3] RFD always on */
64 * 20000ppm/80000ppm. Lock out 2
70 * NOF=40LSB for HBR CDR setting
73 {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
74 {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
77 * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
80 {0x04, 0xc1, 0x92}, /* Gitune=-37% */
81 {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
82 {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
85 * [7:4] LVDS driver bias current :
90 * [7:6] Right-bar GPIO output strength is 8mA
93 /* EQ Training State Machine Setting */
94 {0x04, 0x54, 0x10}, /* RCO calibration start */
95 /* [4:0] MAX_LANE_COUNT set to one lane */
97 /* [4:0] LANE_COUNT_SET set to one lane */
100 {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
102 /* Counter number, add 1ms counter delay */
105 * [6]PWM function control by
106 * DPCD0040f[7], default is PWM
107 * block always works.
111 * 04h Adjust VTotal tolerance to
112 * fix the 30Hz no display issue
115 /* DPCD00400='h00, Parade OUI = 'h001cf8 */
117 {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
118 {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
120 * DPCD403~408 = ASCII code
121 * D2SLV5='h4432534c5635
124 {0x01, 0xc4, 0x32}, /* DPCD404 */
125 {0x01, 0xc5, 0x53}, /* DPCD405 */
126 {0x01, 0xc6, 0x4c}, /* DPCD406 */
127 {0x01, 0xc7, 0x56}, /* DPCD407 */
128 {0x01, 0xc8, 0x35}, /* DPCD408 */
130 * DPCD40A, Initial Code major revision
134 /* DPCD40B, Initial Code minor revision '05' */
136 /* DPCD720, Select internal PWM */
139 * FFh for 100% PWM of brightness, 0h for 0%
144 * Set LVDS output as 6bit-VESA mapping,
145 * single LVDS channel
148 /* Enable SSC set by register */
151 * Set SSC enabled and +/-1% central
155 /* MPU Clock source: LC => RCO */
157 {0x04, 0x54, 0x14}, /* LC -> RCO */
158 {0x02, 0xa1, 0x91}, /* HPD high */
163 * Write values table into the Parade eDP bridge
165 * @return 0 on success, non-0 on failure
168 static int parade_write_regs(int base_addr, const struct reg_data *table)
172 while (!ret && (table->addr_off != END_OF_TABLE)) {
173 ret = i2c_write(base_addr + table->addr_off,
175 (uint8_t *)&table->value,
176 sizeof(table->value));
182 int parade_init(const void *blob)
184 struct gpio_desc rst_gpio;
185 struct gpio_desc slp_gpio;
192 node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625);
196 parent = fdt_parent_offset(blob, node);
198 debug("%s: Could not find parent i2c node\n", __func__);
201 addr = fdtdec_get_int(blob, node, "reg", -1);
203 debug("%s: Could not find i2c address\n", __func__);
207 gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
208 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
212 gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
213 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
215 bus = i2c_get_bus_num_fdt(parent);
216 old_bus = i2c_get_bus_num();
218 debug("%s: Using i2c bus %d\n", __func__, bus);
221 * TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay
225 i2c_set_bus_num(bus);
226 ret = parade_write_regs(addr, parade_values);
228 i2c_set_bus_num(old_bus);