4 * (C) Copyright 2001-2002
5 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
7 * SPDX-License-Identifier: GPL-2.0+
10 /************************************************************************/
12 /************************************************************************/
18 #include <linux/types.h>
19 #include <stdio_dev.h>
21 #include <asm/arch/pxa-regs.h>
28 /*----------------------------------------------------------------------*/
30 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
35 /* LCD outputs connected to a video DAC */
36 # define LCD_BPP LCD_COLOR8
38 /* you have to set lccr0 and lccr3 (including pcd) */
39 # define REG_LCCR0 0x003008f8
40 # define REG_LCCR3 0x0300FF01
42 /* 640x480x16 @ 61 Hz */
43 vidinfo_t panel_info = {
48 .vl_clkp = CONFIG_SYS_HIGH,
49 .vl_oep = CONFIG_SYS_HIGH,
50 .vl_hsp = CONFIG_SYS_HIGH,
51 .vl_vsp = CONFIG_SYS_HIGH,
52 .vl_dp = CONFIG_SYS_HIGH,
65 #endif /* CONFIG_PXA_VIDEO */
67 /*----------------------------------------------------------------------*/
68 #ifdef CONFIG_SHARP_LM8V31
70 # define LCD_BPP LCD_COLOR8
71 # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
73 /* you have to set lccr0 and lccr3 (including pcd) */
74 # define REG_LCCR0 0x0030087C
75 # define REG_LCCR3 0x0340FF08
77 vidinfo_t panel_info = {
82 .vl_clkp = CONFIG_SYS_HIGH,
83 .vl_oep = CONFIG_SYS_HIGH,
84 .vl_hsp = CONFIG_SYS_HIGH,
85 .vl_vsp = CONFIG_SYS_HIGH,
86 .vl_dp = CONFIG_SYS_HIGH,
99 #endif /* CONFIG_SHARP_LM8V31 */
100 /*----------------------------------------------------------------------*/
101 #ifdef CONFIG_VOIPAC_LCD
103 # define LCD_BPP LCD_COLOR8
104 # define LCD_INVERT_COLORS
106 /* you have to set lccr0 and lccr3 (including pcd) */
107 # define REG_LCCR0 0x043008f8
108 # define REG_LCCR3 0x0340FF08
110 vidinfo_t panel_info = {
115 .vl_clkp = CONFIG_SYS_HIGH,
116 .vl_oep = CONFIG_SYS_HIGH,
117 .vl_hsp = CONFIG_SYS_HIGH,
118 .vl_vsp = CONFIG_SYS_HIGH,
119 .vl_dp = CONFIG_SYS_HIGH,
132 #endif /* CONFIG_VOIPAC_LCD */
134 /*----------------------------------------------------------------------*/
135 #ifdef CONFIG_HITACHI_SX14
136 /* Hitachi SX14Q004-ZZA color STN LCD */
137 #define LCD_BPP LCD_COLOR8
139 /* you have to set lccr0 and lccr3 (including pcd) */
140 #define REG_LCCR0 0x00301079
141 #define REG_LCCR3 0x0340FF20
143 vidinfo_t panel_info = {
148 .vl_clkp = CONFIG_SYS_HIGH,
149 .vl_oep = CONFIG_SYS_HIGH,
150 .vl_hsp = CONFIG_SYS_HIGH,
151 .vl_vsp = CONFIG_SYS_HIGH,
152 .vl_dp = CONFIG_SYS_HIGH,
165 #endif /* CONFIG_HITACHI_SX14 */
167 /*----------------------------------------------------------------------*/
168 #ifdef CONFIG_LMS283GF05
170 # define LCD_BPP LCD_COLOR8
171 /*# define LCD_INVERT_COLORS*/
173 /* you have to set lccr0 and lccr3 (including pcd) */
174 # define REG_LCCR0 0x043008f8
175 # define REG_LCCR3 0x03b00009
177 vidinfo_t panel_info = {
182 .vl_clkp = CONFIG_SYS_HIGH,
183 .vl_oep = CONFIG_SYS_LOW,
184 .vl_hsp = CONFIG_SYS_LOW,
185 .vl_vsp = CONFIG_SYS_LOW,
186 .vl_dp = CONFIG_SYS_HIGH,
199 #endif /* CONFIG_LMS283GF05 */
201 /*----------------------------------------------------------------------*/
203 #ifdef CONFIG_ACX517AKN
205 # define LCD_BPP LCD_COLOR8
207 /* you have to set lccr0 and lccr3 (including pcd) */
208 # define REG_LCCR0 0x003008f9
209 # define REG_LCCR3 0x03700006
211 vidinfo_t panel_info = {
216 .vl_clkp = CONFIG_SYS_HIGH,
217 .vl_oep = CONFIG_SYS_LOW,
218 .vl_hsp = CONFIG_SYS_LOW,
219 .vl_vsp = CONFIG_SYS_LOW,
220 .vl_dp = CONFIG_SYS_HIGH,
233 #endif /* CONFIG_ACX517AKN */
235 #ifdef CONFIG_ACX544AKN
237 # define LCD_BPP LCD_COLOR16
239 /* you have to set lccr0 and lccr3 (including pcd) */
240 # define REG_LCCR0 0x003008f9
241 # define REG_LCCR3 0x04700007 /* 16bpp */
243 vidinfo_t panel_info = {
248 .vl_clkp = CONFIG_SYS_LOW,
249 .vl_oep = CONFIG_SYS_LOW,
250 .vl_hsp = CONFIG_SYS_LOW,
251 .vl_vsp = CONFIG_SYS_LOW,
252 .vl_dp = CONFIG_SYS_LOW,
265 #endif /* CONFIG_ACX544AKN */
267 /*----------------------------------------------------------------------*/
269 #ifdef CONFIG_LQ038J7DH53
271 # define LCD_BPP LCD_COLOR8
273 /* you have to set lccr0 and lccr3 (including pcd) */
274 # define REG_LCCR0 0x003008f9
275 # define REG_LCCR3 0x03700004
277 vidinfo_t panel_info = {
282 .vl_clkp = CONFIG_SYS_HIGH,
283 .vl_oep = CONFIG_SYS_LOW,
284 .vl_hsp = CONFIG_SYS_LOW,
285 .vl_vsp = CONFIG_SYS_LOW,
286 .vl_dp = CONFIG_SYS_HIGH,
299 #endif /* CONFIG_ACX517AKN */
301 /*----------------------------------------------------------------------*/
303 #ifdef CONFIG_LITTLETON_LCD
304 # define LCD_BPP LCD_COLOR8
306 /* you have to set lccr0 and lccr3 (including pcd) */
307 # define REG_LCCR0 0x003008f8
308 # define REG_LCCR3 0x0300FF04
310 vidinfo_t panel_info = {
315 .vl_clkp = CONFIG_SYS_HIGH,
316 .vl_oep = CONFIG_SYS_HIGH,
317 .vl_hsp = CONFIG_SYS_HIGH,
318 .vl_vsp = CONFIG_SYS_HIGH,
319 .vl_dp = CONFIG_SYS_HIGH,
332 #endif /* CONFIG_LITTLETON_LCD */
334 /*----------------------------------------------------------------------*/
336 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
337 static void pxafb_setup_gpio (vidinfo_t *vid);
338 static void pxafb_enable_controller (vidinfo_t *vid);
339 static int pxafb_init (vidinfo_t *vid);
341 /************************************************************************/
342 /* --------------- PXA chipset specific functions ------------------- */
343 /************************************************************************/
345 void lcd_ctrl_init (void *lcdbase)
347 pxafb_init_mem(lcdbase, &panel_info);
348 pxafb_init(&panel_info);
349 pxafb_setup_gpio(&panel_info);
350 pxafb_enable_controller(&panel_info);
353 /*----------------------------------------------------------------------*/
354 #if LCD_BPP == LCD_COLOR8
356 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
358 struct pxafb_info *fbi = &panel_info.pxa;
359 unsigned short *palette = (unsigned short *)fbi->palette;
362 if (regno < fbi->palette_size) {
363 val = ((red << 8) & 0xf800);
364 val |= ((green << 4) & 0x07e0);
365 val |= (blue & 0x001f);
367 #ifdef LCD_INVERT_COLORS
368 palette[regno] = ~val;
370 palette[regno] = val;
374 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
375 regno, &palette[regno],
379 #endif /* LCD_COLOR8 */
381 /*----------------------------------------------------------------------*/
382 #if LCD_BPP == LCD_MONOCHROME
383 void lcd_initcolregs (void)
385 struct pxafb_info *fbi = &panel_info.pxa;
386 cmap = (ushort *)fbi->palette;
389 for (regno = 0; regno < 16; regno++) {
391 cmap[(regno * 2) + 1] = regno & 0x0f;
394 #endif /* LCD_MONOCHROME */
396 /*----------------------------------------------------------------------*/
397 __weak void lcd_enable(void)
401 /************************************************************************/
402 /* ** PXA255 specific routines */
403 /************************************************************************/
406 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
407 * descriptors and palette areas.
409 ulong calc_fbsize (void)
412 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
414 size = line_length * panel_info.vl_row;
420 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
422 u_long palette_mem_size;
423 struct pxafb_info *fbi = &vid->pxa;
424 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
426 fbi->screen = (u_long)lcdbase;
428 fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
429 palette_mem_size = fbi->palette_size * sizeof(u16);
431 debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
432 /* locate palette and descs at end of page following fb */
433 fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
437 #ifdef CONFIG_CPU_MONAHANS
438 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
440 static void pxafb_setup_gpio (vidinfo_t *vid)
445 * setup is based on type of panel supported
448 lccr0 = vid->pxa.reg_lccr0;
450 /* 4 bit interface */
451 if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
453 debug("Setting GPIO for 4 bit data\n");
455 writel(readl(GPDR1) | (0xf << 26), GPDR1);
456 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
460 writel(readl(GPDR2) | (0xf << 10), GPDR2);
461 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
465 /* 8 bit interface */
466 else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
467 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
469 debug("Setting GPIO for 8 bit data\n");
471 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
472 writel(readl(GPDR2) | (0x3), GPDR2);
474 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
476 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
479 writel(readl(GPDR2) | (0xf << 10), GPDR2);
480 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
484 /* 16 bit interface */
485 else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
487 debug("Setting GPIO for 16 bit data\n");
489 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
490 writel(readl(GPDR2) | 0x00003fff, GPDR2);
492 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
494 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
498 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
503 static void pxafb_enable_controller (vidinfo_t *vid)
505 debug("Enabling LCD controller\n");
507 /* Sequence from 11.7.10 */
508 writel(vid->pxa.reg_lccr3, LCCR3);
509 writel(vid->pxa.reg_lccr2, LCCR2);
510 writel(vid->pxa.reg_lccr1, LCCR1);
511 writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
512 writel(vid->pxa.fdadr0, FDADR0);
513 writel(vid->pxa.fdadr1, FDADR1);
514 writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
516 #ifdef CONFIG_CPU_MONAHANS
517 writel(readl(CKENA) | CKENA_1_LCD, CKENA);
519 writel(readl(CKEN) | CKEN16_LCD, CKEN);
522 debug("FDADR0 = 0x%08x\n", readl(FDADR0));
523 debug("FDADR1 = 0x%08x\n", readl(FDADR1));
524 debug("LCCR0 = 0x%08x\n", readl(LCCR0));
525 debug("LCCR1 = 0x%08x\n", readl(LCCR1));
526 debug("LCCR2 = 0x%08x\n", readl(LCCR2));
527 debug("LCCR3 = 0x%08x\n", readl(LCCR3));
530 static int pxafb_init (vidinfo_t *vid)
532 struct pxafb_info *fbi = &vid->pxa;
534 debug("Configuring PXA LCD\n");
536 fbi->reg_lccr0 = REG_LCCR0;
537 fbi->reg_lccr3 = REG_LCCR3;
539 debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
540 vid->vl_col, vid->vl_hpw,
541 vid->vl_blw, vid->vl_elw);
542 debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
543 vid->vl_row, vid->vl_vpw,
544 vid->vl_bfw, vid->vl_efw);
547 LCCR1_DisWdth(vid->vl_col) +
548 LCCR1_HorSnchWdth(vid->vl_hpw) +
549 LCCR1_BegLnDel(vid->vl_blw) +
550 LCCR1_EndLnDel(vid->vl_elw);
553 LCCR2_DisHght(vid->vl_row) +
554 LCCR2_VrtSnchWdth(vid->vl_vpw) +
555 LCCR2_BegFrmDel(vid->vl_bfw) +
556 LCCR2_EndFrmDel(vid->vl_efw);
558 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
559 fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
560 | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
563 /* setup dma descriptors */
564 fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
565 fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
566 fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
568 #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
569 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
570 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
572 /* populate descriptors */
573 fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
574 fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
575 fbi->dmadesc_fblow->fidr = 0;
576 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
578 fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
580 fbi->dmadesc_fbhigh->fsadr = fbi->screen;
581 fbi->dmadesc_fbhigh->fidr = 0;
582 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
584 fbi->dmadesc_palette->fsadr = fbi->palette;
585 fbi->dmadesc_palette->fidr = 0;
586 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
588 if( NBITS(vid->vl_bpix) < 12)
590 /* assume any mode with <12 bpp is palette driven */
591 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
592 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
593 /* flips back and forth between pal and fbhigh */
594 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
598 /* palette shouldn't be loaded in true-color mode */
599 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
600 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
603 debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
604 debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
605 debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
607 debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
608 debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
609 debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
611 debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
612 debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
613 debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
615 debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
616 debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
617 debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
622 /************************************************************************/
623 /************************************************************************/
625 #endif /* CONFIG_LCD */