4 * (C) Copyright 2001-2002
5 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
7 * SPDX-License-Identifier: GPL-2.0+
10 /************************************************************************/
12 /************************************************************************/
15 #include <asm/arch/pxa-regs.h>
18 #include <linux/types.h>
20 #include <stdio_dev.h>
26 /*----------------------------------------------------------------------*/
28 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
33 /* LCD outputs connected to a video DAC */
34 # define LCD_BPP LCD_COLOR8
36 /* you have to set lccr0 and lccr3 (including pcd) */
37 # define REG_LCCR0 0x003008f8
38 # define REG_LCCR3 0x0300FF01
40 /* 640x480x16 @ 61 Hz */
41 vidinfo_t panel_info = {
46 .vl_clkp = CONFIG_SYS_HIGH,
47 .vl_oep = CONFIG_SYS_HIGH,
48 .vl_hsp = CONFIG_SYS_HIGH,
49 .vl_vsp = CONFIG_SYS_HIGH,
50 .vl_dp = CONFIG_SYS_HIGH,
63 #endif /* CONFIG_PXA_VIDEO */
65 /*----------------------------------------------------------------------*/
66 #ifdef CONFIG_SHARP_LM8V31
68 # define LCD_BPP LCD_COLOR8
69 # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
71 /* you have to set lccr0 and lccr3 (including pcd) */
72 # define REG_LCCR0 0x0030087C
73 # define REG_LCCR3 0x0340FF08
75 vidinfo_t panel_info = {
80 .vl_clkp = CONFIG_SYS_HIGH,
81 .vl_oep = CONFIG_SYS_HIGH,
82 .vl_hsp = CONFIG_SYS_HIGH,
83 .vl_vsp = CONFIG_SYS_HIGH,
84 .vl_dp = CONFIG_SYS_HIGH,
97 #endif /* CONFIG_SHARP_LM8V31 */
98 /*----------------------------------------------------------------------*/
99 #ifdef CONFIG_VOIPAC_LCD
101 # define LCD_BPP LCD_COLOR8
102 # define LCD_INVERT_COLORS
104 /* you have to set lccr0 and lccr3 (including pcd) */
105 # define REG_LCCR0 0x043008f8
106 # define REG_LCCR3 0x0340FF08
108 vidinfo_t panel_info = {
113 .vl_clkp = CONFIG_SYS_HIGH,
114 .vl_oep = CONFIG_SYS_HIGH,
115 .vl_hsp = CONFIG_SYS_HIGH,
116 .vl_vsp = CONFIG_SYS_HIGH,
117 .vl_dp = CONFIG_SYS_HIGH,
130 #endif /* CONFIG_VOIPAC_LCD */
132 /*----------------------------------------------------------------------*/
133 #ifdef CONFIG_HITACHI_SX14
134 /* Hitachi SX14Q004-ZZA color STN LCD */
135 #define LCD_BPP LCD_COLOR8
137 /* you have to set lccr0 and lccr3 (including pcd) */
138 #define REG_LCCR0 0x00301079
139 #define REG_LCCR3 0x0340FF20
141 vidinfo_t panel_info = {
146 .vl_clkp = CONFIG_SYS_HIGH,
147 .vl_oep = CONFIG_SYS_HIGH,
148 .vl_hsp = CONFIG_SYS_HIGH,
149 .vl_vsp = CONFIG_SYS_HIGH,
150 .vl_dp = CONFIG_SYS_HIGH,
163 #endif /* CONFIG_HITACHI_SX14 */
165 /*----------------------------------------------------------------------*/
166 #ifdef CONFIG_LMS283GF05
168 # define LCD_BPP LCD_COLOR8
169 /*# define LCD_INVERT_COLORS*/
171 /* you have to set lccr0 and lccr3 (including pcd) */
172 # define REG_LCCR0 0x043008f8
173 # define REG_LCCR3 0x03b00009
175 vidinfo_t panel_info = {
181 .vl_clkp = CONFIG_SYS_HIGH,
182 .vl_oep = CONFIG_SYS_LOW,
183 .vl_hsp = CONFIG_SYS_LOW,
184 .vl_vsp = CONFIG_SYS_LOW,
185 .vl_dp = CONFIG_SYS_HIGH,
198 #endif /* CONFIG_LMS283GF05 */
200 /*----------------------------------------------------------------------*/
202 #ifdef CONFIG_ACX517AKN
204 # define LCD_BPP LCD_COLOR8
206 /* you have to set lccr0 and lccr3 (including pcd) */
207 # define REG_LCCR0 0x003008f9
208 # define REG_LCCR3 0x03700006
210 vidinfo_t panel_info = {
215 .vl_clkp = CONFIG_SYS_HIGH,
216 .vl_oep = CONFIG_SYS_LOW,
217 .vl_hsp = CONFIG_SYS_LOW,
218 .vl_vsp = CONFIG_SYS_LOW,
219 .vl_dp = CONFIG_SYS_HIGH,
232 #endif /* CONFIG_ACX517AKN */
234 #ifdef CONFIG_ACX544AKN
236 # define LCD_BPP LCD_COLOR16
238 /* you have to set lccr0 and lccr3 (including pcd) */
239 # define REG_LCCR0 0x003008f9
240 # define REG_LCCR3 0x04700007 /* 16bpp */
242 vidinfo_t panel_info = {
247 .vl_clkp = CONFIG_SYS_LOW,
248 .vl_oep = CONFIG_SYS_LOW,
249 .vl_hsp = CONFIG_SYS_LOW,
250 .vl_vsp = CONFIG_SYS_LOW,
251 .vl_dp = CONFIG_SYS_LOW,
264 #endif /* CONFIG_ACX544AKN */
266 /*----------------------------------------------------------------------*/
268 #ifdef CONFIG_LQ038J7DH53
270 # define LCD_BPP LCD_COLOR8
272 /* you have to set lccr0 and lccr3 (including pcd) */
273 # define REG_LCCR0 0x003008f9
274 # define REG_LCCR3 0x03700004
276 vidinfo_t panel_info = {
281 .vl_clkp = CONFIG_SYS_HIGH,
282 .vl_oep = CONFIG_SYS_LOW,
283 .vl_hsp = CONFIG_SYS_LOW,
284 .vl_vsp = CONFIG_SYS_LOW,
285 .vl_dp = CONFIG_SYS_HIGH,
298 #endif /* CONFIG_ACX517AKN */
300 /*----------------------------------------------------------------------*/
302 #ifdef CONFIG_LITTLETON_LCD
303 # define LCD_BPP LCD_COLOR8
305 /* you have to set lccr0 and lccr3 (including pcd) */
306 # define REG_LCCR0 0x003008f8
307 # define REG_LCCR3 0x0300FF04
309 vidinfo_t panel_info = {
314 .vl_clkp = CONFIG_SYS_HIGH,
315 .vl_oep = CONFIG_SYS_HIGH,
316 .vl_hsp = CONFIG_SYS_HIGH,
317 .vl_vsp = CONFIG_SYS_HIGH,
318 .vl_dp = CONFIG_SYS_HIGH,
331 #endif /* CONFIG_LITTLETON_LCD */
333 /*----------------------------------------------------------------------*/
335 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
336 static void pxafb_setup_gpio (vidinfo_t *vid);
337 static void pxafb_enable_controller (vidinfo_t *vid);
338 static int pxafb_init (vidinfo_t *vid);
340 /************************************************************************/
341 /* --------------- PXA chipset specific functions ------------------- */
342 /************************************************************************/
344 ushort *configuration_get_cmap(void)
346 struct pxafb_info *fbi = &panel_info.pxa;
347 return (ushort *)fbi->palette;
350 void lcd_ctrl_init (void *lcdbase)
352 pxafb_init_mem(lcdbase, &panel_info);
353 pxafb_init(&panel_info);
354 pxafb_setup_gpio(&panel_info);
355 pxafb_enable_controller(&panel_info);
357 /* Enable flushing if we enabled dcache */
358 lcd_set_flush_dcache(1);
361 /*----------------------------------------------------------------------*/
362 #if LCD_BPP == LCD_COLOR8
364 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
366 struct pxafb_info *fbi = &panel_info.pxa;
367 unsigned short *palette = (unsigned short *)fbi->palette;
370 if (regno < fbi->palette_size) {
371 val = ((red << 8) & 0xf800);
372 val |= ((green << 4) & 0x07e0);
373 val |= (blue & 0x001f);
375 #ifdef LCD_INVERT_COLORS
376 palette[regno] = ~val;
378 palette[regno] = val;
382 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
383 regno, &palette[regno],
387 #endif /* LCD_COLOR8 */
389 /*----------------------------------------------------------------------*/
390 __weak void lcd_enable(void)
394 /************************************************************************/
395 /* ** PXA255 specific routines */
396 /************************************************************************/
399 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
400 * descriptors and palette areas.
402 ulong calc_fbsize (void)
405 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
407 size = line_length * panel_info.vl_row;
413 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
415 u_long palette_mem_size;
416 struct pxafb_info *fbi = &vid->pxa;
417 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
419 fbi->screen = (u_long)lcdbase;
421 fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
422 palette_mem_size = fbi->palette_size * sizeof(u16);
424 debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
425 /* locate palette and descs at end of page following fb */
426 fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
430 #ifdef CONFIG_CPU_MONAHANS
431 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
433 static void pxafb_setup_gpio (vidinfo_t *vid)
438 * setup is based on type of panel supported
441 lccr0 = vid->pxa.reg_lccr0;
443 /* 4 bit interface */
444 if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
446 debug("Setting GPIO for 4 bit data\n");
448 writel(readl(GPDR1) | (0xf << 26), GPDR1);
449 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
453 writel(readl(GPDR2) | (0xf << 10), GPDR2);
454 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
458 /* 8 bit interface */
459 else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
460 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
462 debug("Setting GPIO for 8 bit data\n");
464 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
465 writel(readl(GPDR2) | (0x3), GPDR2);
467 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
469 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
472 writel(readl(GPDR2) | (0xf << 10), GPDR2);
473 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
477 /* 16 bit interface */
478 else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
480 debug("Setting GPIO for 16 bit data\n");
482 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
483 writel(readl(GPDR2) | 0x00003fff, GPDR2);
485 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
487 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
491 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
496 static void pxafb_enable_controller (vidinfo_t *vid)
498 debug("Enabling LCD controller\n");
500 /* Sequence from 11.7.10 */
501 writel(vid->pxa.reg_lccr3, LCCR3);
502 writel(vid->pxa.reg_lccr2, LCCR2);
503 writel(vid->pxa.reg_lccr1, LCCR1);
504 writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
505 writel(vid->pxa.fdadr0, FDADR0);
506 writel(vid->pxa.fdadr1, FDADR1);
507 writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
509 #ifdef CONFIG_CPU_MONAHANS
510 writel(readl(CKENA) | CKENA_1_LCD, CKENA);
512 writel(readl(CKEN) | CKEN16_LCD, CKEN);
515 debug("FDADR0 = 0x%08x\n", readl(FDADR0));
516 debug("FDADR1 = 0x%08x\n", readl(FDADR1));
517 debug("LCCR0 = 0x%08x\n", readl(LCCR0));
518 debug("LCCR1 = 0x%08x\n", readl(LCCR1));
519 debug("LCCR2 = 0x%08x\n", readl(LCCR2));
520 debug("LCCR3 = 0x%08x\n", readl(LCCR3));
523 static int pxafb_init (vidinfo_t *vid)
525 struct pxafb_info *fbi = &vid->pxa;
527 debug("Configuring PXA LCD\n");
529 fbi->reg_lccr0 = REG_LCCR0;
530 fbi->reg_lccr3 = REG_LCCR3;
532 debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
533 vid->vl_col, vid->vl_hpw,
534 vid->vl_blw, vid->vl_elw);
535 debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
536 vid->vl_row, vid->vl_vpw,
537 vid->vl_bfw, vid->vl_efw);
540 LCCR1_DisWdth(vid->vl_col) +
541 LCCR1_HorSnchWdth(vid->vl_hpw) +
542 LCCR1_BegLnDel(vid->vl_blw) +
543 LCCR1_EndLnDel(vid->vl_elw);
546 LCCR2_DisHght(vid->vl_row) +
547 LCCR2_VrtSnchWdth(vid->vl_vpw) +
548 LCCR2_BegFrmDel(vid->vl_bfw) +
549 LCCR2_EndFrmDel(vid->vl_efw);
551 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
552 fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
553 | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
556 /* setup dma descriptors */
557 fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
558 fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
559 fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
561 #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
562 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
563 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
565 /* populate descriptors */
566 fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
567 fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
568 fbi->dmadesc_fblow->fidr = 0;
569 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
571 flush_dcache_range((u32)fbi->dmadesc_fblow,
572 (u32)fbi->dmadesc_fblow +
573 sizeof(*fbi->dmadesc_fblow));
575 fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
577 fbi->dmadesc_fbhigh->fsadr = fbi->screen;
578 fbi->dmadesc_fbhigh->fidr = 0;
579 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
581 fbi->dmadesc_palette->fsadr = fbi->palette;
582 fbi->dmadesc_palette->fidr = 0;
583 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
585 if( NBITS(vid->vl_bpix) < 12)
587 /* assume any mode with <12 bpp is palette driven */
588 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
589 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
590 flush_dcache_range((u32)fbi->dmadesc_fbhigh,
591 (u32)fbi->dmadesc_fbhigh +
592 sizeof(*fbi->dmadesc_fbhigh));
593 flush_dcache_range((u32)fbi->dmadesc_palette,
594 (u32)fbi->dmadesc_palette +
595 sizeof(*fbi->dmadesc_palette));
596 /* flips back and forth between pal and fbhigh */
597 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
601 flush_dcache_range((u32)fbi->dmadesc_fbhigh,
602 (u32)fbi->dmadesc_fbhigh +
603 sizeof(*fbi->dmadesc_fbhigh));
604 /* palette shouldn't be loaded in true-color mode */
605 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
606 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
609 debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
610 debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
611 debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
613 debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
614 debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
615 debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
617 debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
618 debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
619 debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
621 debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
622 debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
623 debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
628 /************************************************************************/
629 /************************************************************************/
631 #endif /* CONFIG_LCD */