2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
5 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/edp_rk3288.h>
20 #include <asm/arch/grf_rk3288.h>
21 #include <dt-bindings/clock/rk3288-cru.h>
23 DECLARE_GLOBAL_DATA_PTR;
27 #define DP_LINK_STATUS_SIZE 6
29 static const char * const voltage_names[] = {
30 "0.4V", "0.6V", "0.8V", "1.2V"
32 static const char * const pre_emph_names[] = {
33 "0dB", "3.5dB", "6dB", "9.5dB"
36 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
37 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
40 struct rk3288_edp *regs;
41 struct rk3288_grf *grf;
42 struct udevice *panel;
43 struct link_train link_train;
47 static void rk_edp_init_refclk(struct rk3288_edp *regs)
49 writel(SEL_24M, ®s->analog_ctl_2);
50 writel(REF_CLK_24M, ®s->pll_reg_1);
52 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
53 V2L_CUR_SEL_1MA, ®s->pll_reg_2);
55 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
56 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
59 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
60 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
63 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg);
65 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
66 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
69 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
72 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
75 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
79 static void rk_edp_init_interrupt(struct rk3288_edp *regs)
81 /* Set interrupt pin assertion polarity as high */
82 writel(INT_POL, ®s->int_ctl);
84 /* Clear pending registers */
85 writel(0xff, ®s->common_int_sta_1);
86 writel(0x4f, ®s->common_int_sta_2);
87 writel(0xff, ®s->common_int_sta_3);
88 writel(0x27, ®s->common_int_sta_4);
89 writel(0x7f, ®s->dp_int_sta);
91 /* 0:mask,1: unmask */
92 writel(0x00, ®s->common_int_mask_1);
93 writel(0x00, ®s->common_int_mask_2);
94 writel(0x00, ®s->common_int_mask_3);
95 writel(0x00, ®s->common_int_mask_4);
96 writel(0x00, ®s->int_sta_mask);
99 static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
101 clrbits_le32(®s->func_en_1, SW_FUNC_EN_N);
104 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
108 val = readl(®s->dp_debug_ctl);
110 return val & PLL_LOCK;
113 static int rk_edp_init_analog_func(struct rk3288_edp *regs)
117 writel(0x00, ®s->dp_pd);
118 writel(PLL_LOCK_CHG, ®s->common_int_sta_1);
120 clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
122 start = get_timer(0);
123 while (!rk_edp_get_pll_locked(regs)) {
124 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
125 printf("%s: PLL is not locked\n", __func__);
130 /* Enable Serdes FIFO function and Link symbol clock domain module */
131 clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N |
132 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
138 static void rk_edp_init_aux(struct rk3288_edp *regs)
140 /* Clear inerrupts related to AUX channel */
141 writel(AUX_FUNC_EN_N, ®s->dp_int_sta);
143 /* Disable AUX channel module */
144 setbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
146 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
147 writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl);
149 /* Enable AUX channel module */
150 clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
153 static int rk_edp_aux_enable(struct rk3288_edp *regs)
157 setbits_le32(®s->aux_ch_ctl_2, AUX_EN);
158 start = get_timer(0);
160 if (!(readl(®s->aux_ch_ctl_2) & AUX_EN))
162 } while (get_timer(start) < 20);
167 static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
171 start = get_timer(0);
172 while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) {
173 if (get_timer(start) > 10)
177 writel(RPLY_RECEIV, ®s->dp_int_sta);
182 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
186 /* Enable AUX CH operation */
187 ret = rk_edp_aux_enable(regs);
189 debug("AUX CH enable timeout!\n");
193 /* Is AUX CH command reply received? */
194 if (rk_edp_is_aux_reply(regs)) {
195 debug("AUX CH command reply failed!\n");
199 /* Clear interrupt source for AUX CH access error */
200 val = readl(®s->dp_int_sta);
202 writel(AUX_ERR, ®s->dp_int_sta);
206 /* Check AUX CH error access status */
207 val = readl(®s->dp_int_sta);
208 if (val & AUX_STATUS_MASK) {
209 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
216 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
217 unsigned int val_addr, u8 *in_data,
219 enum dpcd_request request)
228 len = min(length, 16U);
229 for (try_times = 0; try_times < 10; try_times++) {
231 /* Clear AUX CH data buffer */
232 writel(BUF_CLR, ®s->buf_data_ctl);
234 /* Select DPCD device address */
235 writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0);
236 writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8);
237 writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16);
240 * Set DisplayPort transaction and read 1 byte
241 * If bit 3 is 1, DisplayPort transaction.
242 * If Bit 3 is 0, I2C transaction.
244 if (request == DPCD_WRITE) {
245 val = AUX_LENGTH(len) |
246 AUX_TX_COMM_DP_TRANSACTION |
248 for (i = 0; i < len; i++)
249 writel(*data++, ®s->buf_data[i]);
251 val = AUX_LENGTH(len) |
252 AUX_TX_COMM_DP_TRANSACTION |
255 writel(val, ®s->aux_ch_ctl_1);
257 /* Start AUX transaction */
258 ret = rk_edp_start_aux_transaction(regs);
262 printf("read dpcd Aux Transaction fail!\n");
268 if (request == DPCD_READ) {
269 for (i = 0; i < len; i++)
270 *data++ = (u8)readl(®s->buf_data[i]);
281 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
284 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
287 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
290 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
294 static int rk_edp_link_power_up(struct rk_edp_priv *edp)
299 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
300 if (edp->link_train.revision < 0x11)
303 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
307 value &= ~DP_SET_POWER_MASK;
308 value |= DP_SET_POWER_D0;
310 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
315 * According to the DP 1.1 specification, a "Sink Device must exit the
316 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
317 * Control Field" (register 0x600).
324 static int rk_edp_link_configure(struct rk_edp_priv *edp)
328 values[0] = edp->link_train.link_rate;
329 values[1] = edp->link_train.lane_count;
331 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
335 static void rk_edp_set_link_training(struct rk_edp_priv *edp,
336 const u8 *training_values)
340 for (i = 0; i < edp->link_train.lane_count; i++)
341 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
344 static u8 edp_link_status(const u8 *link_status, int r)
346 return link_status[r - DPCD_LANE0_1_STATUS];
349 static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
352 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
353 DP_LINK_STATUS_SIZE);
356 static u8 edp_get_lane_status(const u8 *link_status, int lane)
358 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
359 int s = (lane & 1) * 4;
360 u8 l = edp_link_status(link_status, i);
362 return (l >> s) & 0xf;
365 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
370 for (lane = 0; lane < lane_count; lane++) {
371 lane_status = edp_get_lane_status(link_status, lane);
372 if ((lane_status & DP_LANE_CR_DONE) == 0)
379 static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
385 lane_align = edp_link_status(link_status,
386 DPCD_LANE_ALIGN_STATUS_UPDATED);
387 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
389 for (lane = 0; lane < lane_count; lane++) {
390 lane_status = edp_get_lane_status(link_status, lane);
391 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
398 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
400 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
401 int s = ((lane & 1) ?
402 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
403 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
404 u8 l = edp_link_status(link_status, i);
406 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
409 static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
412 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
413 int s = ((lane & 1) ?
414 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
415 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
416 u8 l = edp_link_status(link_status, i);
418 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
421 static void edp_get_adjust_train(const u8 *link_status, int lane_count,
428 for (lane = 0; lane < lane_count; lane++) {
431 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
432 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
435 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
437 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
438 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
446 if (v >= DP_VOLTAGE_MAX)
447 v |= DP_TRAIN_MAX_SWING_REACHED;
449 if (p >= DP_PRE_EMPHASIS_MAX)
450 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
452 debug("using signal parameters: voltage %s pre_emph %s\n",
453 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
454 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
455 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
456 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
458 for (lane = 0; lane < 4; lane++)
459 train_set[lane] = v | p;
462 static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
464 struct rk3288_edp *regs = edp->regs;
466 uint voltage, tries = 0;
467 u8 status[DP_LINK_STATUS_SIZE];
471 value = DP_TRAINING_PATTERN_1;
472 writel(value, ®s->dp_training_ptn_set);
473 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
476 memset(edp->train_set, '\0', sizeof(edp->train_set));
478 /* clock recovery loop */
484 rk_edp_set_link_training(edp, edp->train_set);
485 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
487 edp->link_train.lane_count);
493 ret = rk_edp_dpcd_read_link_status(edp, status);
495 printf("displayport link status failed, ret=%d\n", ret);
499 clock_recovery = rk_edp_clock_recovery(status,
500 edp->link_train.lane_count);
504 for (i = 0; i < edp->link_train.lane_count; i++) {
505 if ((edp->train_set[i] &
506 DP_TRAIN_MAX_SWING_REACHED) == 0)
509 if (i == edp->link_train.lane_count) {
510 printf("clock recovery reached max voltage\n");
514 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
516 if (++tries == MAX_CR_LOOP) {
517 printf("clock recovery tried 5 times\n");
524 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
526 /* Compute new train_set as requested by sink */
527 edp_get_adjust_train(status, edp->link_train.lane_count,
530 if (clock_recovery) {
531 printf("clock recovery failed: %d\n", clock_recovery);
532 return clock_recovery;
534 debug("clock recovery at voltage %d pre-emphasis %d\n",
535 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
536 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
537 DP_TRAIN_PRE_EMPHASIS_SHIFT);
542 static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
544 struct rk3288_edp *regs = edp->regs;
548 u8 status[DP_LINK_STATUS_SIZE];
551 value = DP_TRAINING_PATTERN_2;
552 writel(value, ®s->dp_training_ptn_set);
553 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
557 /* channel equalization loop */
559 for (tries = 0; tries < 5; tries++) {
560 rk_edp_set_link_training(edp, edp->train_set);
563 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
564 printf("displayport link status failed\n");
568 channel_eq = rk_edp_channel_eq(status,
569 edp->link_train.lane_count);
572 edp_get_adjust_train(status, edp->link_train.lane_count,
577 printf("channel eq failed, ret=%d\n", channel_eq);
581 debug("channel eq at voltage %d pre-emphasis %d\n",
582 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
583 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
584 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
589 static int rk_edp_init_training(struct rk_edp_priv *edp)
594 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
599 edp->link_train.revision = values[0];
600 edp->link_train.link_rate = values[1];
601 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
603 debug("max link rate:%d.%dGps max number of lanes:%d\n",
604 edp->link_train.link_rate * 27 / 100,
605 edp->link_train.link_rate * 27 % 100,
606 edp->link_train.lane_count);
608 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
609 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
610 debug("Rx Max Link Rate is abnormal :%x\n",
611 edp->link_train.link_rate);
615 if (edp->link_train.lane_count == 0) {
616 debug("Rx Max Lane count is abnormal :%x\n",
617 edp->link_train.lane_count);
621 ret = rk_edp_link_power_up(edp);
625 return rk_edp_link_configure(edp);
628 static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
634 /* Set link rate and count as you want to establish */
635 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
636 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
638 ret = rk_edp_link_train_cr(edp);
641 ret = rk_edp_link_train_ce(edp);
645 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
646 start = get_timer(0);
648 val = readl(&edp->regs->dp_hw_link_training);
649 if (!(val & HW_LT_EN))
651 } while (get_timer(start) < 10);
653 if (val & HW_LT_ERR_CODE_MASK) {
654 printf("edp hw link training error: %d\n",
655 val >> HW_LT_ERR_CODE_SHIFT);
662 static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
663 unsigned int device_addr,
664 unsigned int val_addr)
668 /* Set EDID device address */
669 writel(device_addr, ®s->aux_addr_7_0);
670 writel(0x0, ®s->aux_addr_15_8);
671 writel(0x0, ®s->aux_addr_19_16);
673 /* Set offset from base address of EDID device */
674 writel(val_addr, ®s->buf_data[0]);
677 * Set I2C transaction and write address
678 * If bit 3 is 1, DisplayPort transaction.
679 * If Bit 3 is 0, I2C transaction.
681 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
682 AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1);
684 /* Start AUX transaction */
685 ret = rk_edp_start_aux_transaction(regs);
687 debug("select_i2c_device Aux Transaction fail!\n");
694 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
695 unsigned int val_addr, unsigned int count, u8 edid[])
699 unsigned int cur_data_idx;
700 unsigned int defer = 0;
703 for (i = 0; i < count; i += 16) {
704 for (j = 0; j < 10; j++) { /* try 10 times */
705 /* Clear AUX CH data buffer */
706 writel(BUF_CLR, ®s->buf_data_ctl);
708 /* Set normal AUX CH command */
709 clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY);
712 * If Rx sends defer, Tx sends only reads
713 * request without sending addres
716 ret = rk_edp_select_i2c_device(regs,
724 * Set I2C transaction and write data
725 * If bit 3 is 1, DisplayPort transaction.
726 * If Bit 3 is 0, I2C transaction.
728 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
729 AUX_TX_COMM_READ, ®s->aux_ch_ctl_1);
731 /* Start AUX transaction */
732 ret = rk_edp_start_aux_transaction(regs);
736 debug("Aux Transaction fail!\n");
740 /* Check if Rx sends defer */
741 val = readl(®s->aux_rx_comm);
742 if (val == AUX_RX_COMM_AUX_DEFER ||
743 val == AUX_RX_COMM_I2C_DEFER) {
744 debug("Defer: %d\n\n", val);
752 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
753 val = readl(®s->buf_data[cur_data_idx]);
754 edid[i + cur_data_idx] = (u8)val;
761 static int rk_edp_set_link_train(struct rk_edp_priv *edp)
765 ret = rk_edp_init_training(edp);
767 printf("DP LT init failed!\n");
771 ret = rk_edp_hw_link_training(edp);
778 static void rk_edp_init_video(struct rk3288_edp *regs)
780 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
781 ®s->common_int_sta_1);
782 writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2);
783 writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8);
786 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
788 clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
791 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
792 enum clock_recovery_m_value_type type,
796 if (type == REGISTER_M) {
797 setbits_le32(®s->sys_ctl_4, FIX_M_VID);
798 writel(m_value & 0xff, ®s->m_vid_0);
799 writel((m_value >> 8) & 0xff, ®s->m_vid_1);
800 writel((m_value >> 16) & 0xff, ®s->m_vid_2);
802 writel(n_value & 0xf, ®s->n_vid_0);
803 writel((n_value >> 8) & 0xff, ®s->n_vid_1);
804 writel((n_value >> 16) & 0xff, ®s->n_vid_2);
806 clrbits_le32(®s->sys_ctl_4, FIX_M_VID);
808 writel(0x00, ®s->n_vid_0);
809 writel(0x80, ®s->n_vid_1);
810 writel(0x00, ®s->n_vid_2);
814 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
819 start = get_timer(0);
821 val = readl(®s->sys_ctl_1);
823 /* must write value to update DET_STA bit status */
824 writel(val, ®s->sys_ctl_1);
825 val = readl(®s->sys_ctl_1);
826 if (!(val & DET_STA))
829 val = readl(®s->sys_ctl_2);
831 /* must write value to update CHA_STA bit status */
832 writel(val, ®s->sys_ctl_2);
833 val = readl(®s->sys_ctl_2);
834 if (!(val & CHA_STA))
837 } while (get_timer(start) < 100);
842 static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
847 start = get_timer(0);
849 val = readl(&edp->regs->sys_ctl_3);
851 /* must write value to update STRM_VALID bit status */
852 writel(val, &edp->regs->sys_ctl_3);
854 val = readl(&edp->regs->sys_ctl_3);
855 if (!(val & STRM_VALID))
857 } while (get_timer(start) < 100);
862 static int rk_edp_config_video(struct rk_edp_priv *edp)
866 rk_edp_config_video_slave_mode(edp->regs);
868 if (!rk_edp_get_pll_locked(edp->regs)) {
869 debug("PLL is not locked yet.\n");
873 ret = rk_edp_is_video_stream_clock_on(edp->regs);
877 /* Set to use the register calculated M/N video */
878 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
880 /* For video bist, Video timing must be generated by register */
881 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
883 /* Disable video mute */
884 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
886 /* Enable video at next frame */
887 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
889 return rk_edp_is_video_stream_on(edp);
892 static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
894 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
897 static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
901 val = readl(&edp->regs->sys_ctl_3);
902 if (val & HPD_STATUS)
909 * support edp HPD function
910 * some hardware version do not support edp hdp,
911 * we use 200ms to try to get the hpd single now,
912 * if we can not get edp hpd single, it will delay 200ms,
913 * also meet the edp power timing request, to compatible
914 * all of the hardware version
916 static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
920 start = get_timer(0);
922 if (rockchip_edp_get_plug_in_status(edp))
925 } while (get_timer(start) < 200);
927 debug("do not get hpd single, force hpd\n");
928 rockchip_edp_force_hpd(edp);
931 static int rk_edp_enable(struct udevice *dev, int panel_bpp,
932 const struct display_timing *edid)
934 struct rk_edp_priv *priv = dev_get_priv(dev);
937 ret = rk_edp_set_link_train(priv);
939 printf("link train failed!\n");
943 rk_edp_init_video(priv->regs);
944 ret = rk_edp_config_video(priv);
946 printf("config video failed\n");
949 ret = panel_enable_backlight(priv->panel);
951 debug("%s: backlight error: %d\n", __func__, ret);
958 static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
960 struct rk_edp_priv *priv = dev_get_priv(dev);
961 u32 edid_size = EDID_LENGTH;
965 for (i = 0; i < 3; i++) {
966 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
967 EDID_LENGTH, &buf[EDID_HEADER]);
969 debug("EDID read failed\n");
974 * check if the EDID has an extension flag, and read additional
975 * EDID data if needed
977 if (buf[EDID_EXTENSION_FLAG]) {
978 edid_size += EDID_LENGTH;
979 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
980 EDID_LENGTH, EDID_LENGTH,
983 debug("EDID Read failed!\n");
990 /* After 3 attempts, give up */
997 static int rk_edp_ofdata_to_platdata(struct udevice *dev)
999 struct rk_edp_priv *priv = dev_get_priv(dev);
1001 priv->regs = (struct rk3288_edp *)dev_get_addr(dev);
1002 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1007 int rk_edp_probe(struct udevice *dev)
1009 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
1010 struct rk_edp_priv *priv = dev_get_priv(dev);
1011 struct rk3288_edp *regs = priv->regs;
1015 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1018 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1023 int vop_id = uc_plat->source_id;
1024 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1026 ret = clk_get_by_index(dev, 1, &clk);
1028 ret = clk_set_rate(&clk, 0);
1032 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1036 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1038 ret = clk_set_rate(&clk, 192000000);
1042 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1043 __func__, uc_plat->src_dev->name, ret);
1047 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1048 rk_setreg(&priv->grf->soc_con12, 1 << 4);
1050 /* select epd signal from vop0 or vop1 */
1051 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
1053 rockchip_edp_wait_hpd(priv);
1055 rk_edp_init_refclk(regs);
1056 rk_edp_init_interrupt(regs);
1057 rk_edp_enable_sw_function(regs);
1058 ret = rk_edp_init_analog_func(regs);
1061 rk_edp_init_aux(regs);
1066 static const struct dm_display_ops dp_rockchip_ops = {
1067 .read_edid = rk_edp_read_edid,
1068 .enable = rk_edp_enable,
1071 static const struct udevice_id rockchip_dp_ids[] = {
1072 { .compatible = "rockchip,rk3288-edp" },
1076 U_BOOT_DRIVER(dp_rockchip) = {
1077 .name = "edp_rockchip",
1078 .id = UCLASS_DISPLAY,
1079 .of_match = rockchip_dp_ids,
1080 .ops = &dp_rockchip_ops,
1081 .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
1082 .probe = rk_edp_probe,
1083 .priv_auto_alloc_size = sizeof(struct rk_edp_priv),