git.sur5r.net Git - u-boot/blob - drivers/video/rockchip/rk_edp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2015 Google, Inc
   4  * Copyright 2014 Rockchip Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <display.h>
  10 #include <dm.h>
  11 #include <edid.h>
  12 #include <panel.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/edp_rk3288.h>
  19 #include <asm/arch/grf_rk3288.h>
  20 #include <dt-bindings/clock/rk3288-cru.h>
  21
  22 #define MAX_CR_LOOP 5
  23 #define MAX_EQ_LOOP 5
  24 #define DP_LINK_STATUS_SIZE 6
  25
  26 static const char * const voltage_names[] = {
  27         "0.4V", "0.6V", "0.8V", "1.2V"
  28 };
  29 static const char * const pre_emph_names[] = {
  30         "0dB", "3.5dB", "6dB", "9.5dB"
  31 };
  32
  33 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
  34 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
  35
  36 struct rk_edp_priv {
  37         struct rk3288_edp *regs;
  38         struct rk3288_grf *grf;
  39         struct udevice *panel;
  40         struct link_train link_train;
  41         u8 train_set[4];
  42 };
  43
  44 static void rk_edp_init_refclk(struct rk3288_edp *regs)
  45 {
  46         writel(SEL_24M, &regs->analog_ctl_2);
  47         writel(REF_CLK_24M, &regs->pll_reg_1);
  48
  49         writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
  50                V2L_CUR_SEL_1MA, &regs->pll_reg_2);
  51
  52         writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
  53                LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
  54                &regs->pll_reg_3);
  55
  56         writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
  57                CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
  58                &regs->pll_reg_5);
  59
  60         writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &regs->ssc_reg);
  61
  62         writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
  63                LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
  64                &regs->tx_common);
  65
  66         writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
  67                &regs->dp_aux);
  68
  69         writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
  70                &regs->dp_bias);
  71
  72         writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
  73                &regs->dp_reserv2);
  74 }
  75
  76 static void rk_edp_init_interrupt(struct rk3288_edp *regs)
  77 {
  78         /* Set interrupt pin assertion polarity as high */
  79         writel(INT_POL, &regs->int_ctl);
  80
  81         /* Clear pending registers */
  82         writel(0xff, &regs->common_int_sta_1);
  83         writel(0x4f, &regs->common_int_sta_2);
  84         writel(0xff, &regs->common_int_sta_3);
  85         writel(0x27, &regs->common_int_sta_4);
  86         writel(0x7f, &regs->dp_int_sta);
  87
  88         /* 0:mask,1: unmask */
  89         writel(0x00, &regs->common_int_mask_1);
  90         writel(0x00, &regs->common_int_mask_2);
  91         writel(0x00, &regs->common_int_mask_3);
  92         writel(0x00, &regs->common_int_mask_4);
  93         writel(0x00, &regs->int_sta_mask);
  94 }
  95
  96 static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
  97 {
  98         clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
  99 }
 100
 101 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
 102 {
 103         u32 val;
 104
 105         val = readl(&regs->dp_debug_ctl);
 106
 107         return val & PLL_LOCK;
 108 }
 109
 110 static int rk_edp_init_analog_func(struct rk3288_edp *regs)
 111 {
 112         ulong start;
 113
 114         writel(0x00, &regs->dp_pd);
 115         writel(PLL_LOCK_CHG, &regs->common_int_sta_1);
 116
 117         clrbits_le32(&regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
 118
 119         start = get_timer(0);
 120         while (!rk_edp_get_pll_locked(regs)) {
 121                 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
 122                         printf("%s: PLL is not locked\n", __func__);
 123                         return -ETIMEDOUT;
 124                 }
 125         }
 126
 127         /* Enable Serdes FIFO function and Link symbol clock domain module */
 128         clrbits_le32(&regs->func_en_2, SERDES_FIFO_FUNC_EN_N |
 129                                        LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
 130                                        SSC_FUNC_EN_N);
 131
 132         return 0;
 133 }
 134
 135 static void rk_edp_init_aux(struct rk3288_edp *regs)
 136 {
 137         /* Clear inerrupts related to AUX channel */
 138         writel(AUX_FUNC_EN_N, &regs->dp_int_sta);
 139
 140         /* Disable AUX channel module */
 141         setbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
 142
 143         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 144         writel(DEFER_CTRL_EN | DEFER_COUNT(1), &regs->aux_ch_defer_dtl);
 145
 146         /* Enable AUX channel module */
 147         clrbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
 148 }
 149
 150 static int rk_edp_aux_enable(struct rk3288_edp *regs)
 151 {
 152         ulong start;
 153
 154         setbits_le32(&regs->aux_ch_ctl_2, AUX_EN);
 155         start = get_timer(0);
 156         do {
 157                 if (!(readl(&regs->aux_ch_ctl_2) & AUX_EN))
 158                         return 0;
 159         } while (get_timer(start) < 20);
 160
 161         return -ETIMEDOUT;
 162 }
 163
 164 static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
 165 {
 166         ulong start;
 167
 168         start = get_timer(0);
 169         while (!(readl(&regs->dp_int_sta) & RPLY_RECEIV)) {
 170                 if (get_timer(start) > 10)
 171                         return -ETIMEDOUT;
 172         }
 173
 174         writel(RPLY_RECEIV, &regs->dp_int_sta);
 175
 176         return 0;
 177 }
 178
 179 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
 180 {
 181         int val, ret;
 182
 183         /* Enable AUX CH operation */
 184         ret = rk_edp_aux_enable(regs);
 185         if (ret) {
 186                 debug("AUX CH enable timeout!\n");
 187                 return ret;
 188         }
 189
 190         /* Is AUX CH command reply received? */
 191         if (rk_edp_is_aux_reply(regs)) {
 192                 debug("AUX CH command reply failed!\n");
 193                 return ret;
 194         }
 195
 196         /* Clear interrupt source for AUX CH access error */
 197         val = readl(&regs->dp_int_sta);
 198         if (val & AUX_ERR) {
 199                 writel(AUX_ERR, &regs->dp_int_sta);
 200                 return -EIO;
 201         }
 202
 203         /* Check AUX CH error access status */
 204         val = readl(&regs->dp_int_sta);
 205         if (val & AUX_STATUS_MASK) {
 206                 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
 207                 return -EIO;
 208         }
 209
 210         return 0;
 211 }
 212
 213 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
 214                                 unsigned int val_addr, u8 *in_data,
 215                                 unsigned int length,
 216                                 enum dpcd_request request)
 217 {
 218         int val;
 219         int i, try_times;
 220         u8 *data;
 221         int ret = 0;
 222         u32 len = 0;
 223
 224         while (length) {
 225                 len = min(length, 16U);
 226                 for (try_times = 0; try_times < 10; try_times++) {
 227                         data = in_data;
 228                         /* Clear AUX CH data buffer */
 229                         writel(BUF_CLR, &regs->buf_data_ctl);
 230
 231                         /* Select DPCD device address */
 232                         writel(AUX_ADDR_7_0(val_addr), &regs->aux_addr_7_0);
 233                         writel(AUX_ADDR_15_8(val_addr), &regs->aux_addr_15_8);
 234                         writel(AUX_ADDR_19_16(val_addr), &regs->aux_addr_19_16);
 235
 236                         /*
 237                          * Set DisplayPort transaction and read 1 byte
 238                          * If bit 3 is 1, DisplayPort transaction.
 239                          * If Bit 3 is 0, I2C transaction.
 240                          */
 241                         if (request == DPCD_WRITE) {
 242                                 val = AUX_LENGTH(len) |
 243                                         AUX_TX_COMM_DP_TRANSACTION |
 244                                         AUX_TX_COMM_WRITE;
 245                                 for (i = 0; i < len; i++)
 246                                         writel(*data++, &regs->buf_data[i]);
 247                         } else
 248                                 val = AUX_LENGTH(len) |
 249                                         AUX_TX_COMM_DP_TRANSACTION |
 250                                         AUX_TX_COMM_READ;
 251
 252                         writel(val, &regs->aux_ch_ctl_1);
 253
 254                         /* Start AUX transaction */
 255                         ret = rk_edp_start_aux_transaction(regs);
 256                         if (ret == 0)
 257                                 break;
 258                         else
 259                                 printf("read dpcd Aux Transaction fail!\n");
 260                 }
 261
 262                 if (ret)
 263                         return ret;
 264
 265                 if (request == DPCD_READ) {
 266                         for (i = 0; i < len; i++)
 267                                 *data++ = (u8)readl(&regs->buf_data[i]);
 268                 }
 269
 270                 length -= len;
 271                 val_addr += len;
 272                 in_data += len;
 273         }
 274
 275         return 0;
 276 }
 277
 278 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
 279                             size_t size)
 280 {
 281         return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
 282 }
 283
 284 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
 285                              size_t size)
 286 {
 287         return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
 288 }
 289
 290
 291 static int rk_edp_link_power_up(struct rk_edp_priv *edp)
 292 {
 293         u8 value;
 294         int ret;
 295
 296         /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 297         if (edp->link_train.revision < 0x11)
 298                 return 0;
 299
 300         ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
 301         if (ret)
 302                 return ret;
 303
 304         value &= ~DP_SET_POWER_MASK;
 305         value |= DP_SET_POWER_D0;
 306
 307         ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
 308         if (ret)
 309                 return ret;
 310
 311         /*
 312          * According to the DP 1.1 specification, a "Sink Device must exit the
 313          * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
 314          * Control Field" (register 0x600).
 315          */
 316         mdelay(1);
 317
 318         return 0;
 319 }
 320
 321 static int rk_edp_link_configure(struct rk_edp_priv *edp)
 322 {
 323         u8 values[2];
 324
 325         values[0] = edp->link_train.link_rate;
 326         values[1] = edp->link_train.lane_count;
 327
 328         return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
 329                                  sizeof(values));
 330 }
 331
 332 static void rk_edp_set_link_training(struct rk_edp_priv *edp,
 333                                      const u8 *training_values)
 334 {
 335         int i;
 336
 337         for (i = 0; i < edp->link_train.lane_count; i++)
 338                 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
 339 }
 340
 341 static u8 edp_link_status(const u8 *link_status, int r)
 342 {
 343         return link_status[r - DPCD_LANE0_1_STATUS];
 344 }
 345
 346 static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
 347                                         u8 *link_status)
 348 {
 349         return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
 350                                 DP_LINK_STATUS_SIZE);
 351 }
 352
 353 static u8 edp_get_lane_status(const u8 *link_status, int lane)
 354 {
 355         int i = DPCD_LANE0_1_STATUS + (lane >> 1);
 356         int s = (lane & 1) * 4;
 357         u8 l = edp_link_status(link_status, i);
 358
 359         return (l >> s) & 0xf;
 360 }
 361
 362 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
 363 {
 364         int lane;
 365         u8 lane_status;
 366
 367         for (lane = 0; lane < lane_count; lane++) {
 368                 lane_status = edp_get_lane_status(link_status, lane);
 369                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 370                         return -EIO;
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
 377 {
 378         u8 lane_align;
 379         u8 lane_status;
 380         int lane;
 381
 382         lane_align = edp_link_status(link_status,
 383                                     DPCD_LANE_ALIGN_STATUS_UPDATED);
 384         if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
 385                 return -EIO;
 386         for (lane = 0; lane < lane_count; lane++) {
 387                 lane_status = edp_get_lane_status(link_status, lane);
 388                 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
 389                         return -EIO;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
 396 {
 397         int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 398         int s = ((lane & 1) ?
 399                  DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 400                  DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 401         u8 l = edp_link_status(link_status, i);
 402
 403         return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 404 }
 405
 406 static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
 407                                                    int lane)
 408 {
 409         int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 410         int s = ((lane & 1) ?
 411                  DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 412                  DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 413         u8 l = edp_link_status(link_status, i);
 414
 415         return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 416 }
 417
 418 static void edp_get_adjust_train(const u8 *link_status, int lane_count,
 419                                  u8 train_set[])
 420 {
 421         uint v = 0;
 422         uint p = 0;
 423         int lane;
 424
 425         for (lane = 0; lane < lane_count; lane++) {
 426                 uint this_v, this_p;
 427
 428                 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
 429                 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
 430                                                                 lane);
 431
 432                 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 433                       lane,
 434                       voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 435                       pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 436
 437                 if (this_v > v)
 438                         v = this_v;
 439                 if (this_p > p)
 440                         p = this_p;
 441         }
 442
 443         if (v >= DP_VOLTAGE_MAX)
 444                 v |= DP_TRAIN_MAX_SWING_REACHED;
 445
 446         if (p >= DP_PRE_EMPHASIS_MAX)
 447                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 448
 449         debug("using signal parameters: voltage %s pre_emph %s\n",
 450               voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
 451                         >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 452               pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
 453                         >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 454
 455         for (lane = 0; lane < 4; lane++)
 456                 train_set[lane] = v | p;
 457 }
 458
 459 static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
 460 {
 461         struct rk3288_edp *regs = edp->regs;
 462         int clock_recovery;
 463         uint voltage, tries = 0;
 464         u8 status[DP_LINK_STATUS_SIZE];
 465         int i, ret;
 466         u8 value;
 467
 468         value = DP_TRAINING_PATTERN_1;
 469         writel(value, &regs->dp_training_ptn_set);
 470         ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
 471         if (ret)
 472                 return ret;
 473         memset(edp->train_set, '\0', sizeof(edp->train_set));
 474
 475         /* clock recovery loop */
 476         clock_recovery = 0;
 477         tries = 0;
 478         voltage = 0xff;
 479
 480         while (1) {
 481                 rk_edp_set_link_training(edp, edp->train_set);
 482                 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
 483                                         edp->train_set,
 484                                         edp->link_train.lane_count);
 485                 if (ret)
 486                         return ret;
 487
 488                 mdelay(1);
 489
 490                 ret = rk_edp_dpcd_read_link_status(edp, status);
 491                 if (ret) {
 492                         printf("displayport link status failed, ret=%d\n", ret);
 493                         break;
 494                 }
 495
 496                 clock_recovery = rk_edp_clock_recovery(status,
 497                                                 edp->link_train.lane_count);
 498                 if (!clock_recovery)
 499                         break;
 500
 501                 for (i = 0; i < edp->link_train.lane_count; i++) {
 502                         if ((edp->train_set[i] &
 503                                 DP_TRAIN_MAX_SWING_REACHED) == 0)
 504                                 break;
 505                 }
 506                 if (i == edp->link_train.lane_count) {
 507                         printf("clock recovery reached max voltage\n");
 508                         break;
 509                 }
 510
 511                 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 512                                 voltage) {
 513                         if (++tries == MAX_CR_LOOP) {
 514                                 printf("clock recovery tried 5 times\n");
 515                                 break;
 516                         }
 517                 } else {
 518                         tries = 0;
 519                 }
 520
 521                 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 522
 523                 /* Compute new train_set as requested by sink */
 524                 edp_get_adjust_train(status, edp->link_train.lane_count,
 525                                      edp->train_set);
 526         }
 527         if (clock_recovery) {
 528                 printf("clock recovery failed: %d\n", clock_recovery);
 529                 return clock_recovery;
 530         } else {
 531                 debug("clock recovery at voltage %d pre-emphasis %d\n",
 532                       edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 533                       (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 534                                 DP_TRAIN_PRE_EMPHASIS_SHIFT);
 535                 return 0;
 536         }
 537 }
 538
 539 static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
 540 {
 541         struct rk3288_edp *regs = edp->regs;
 542         int channel_eq;
 543         u8 value;
 544         int tries;
 545         u8 status[DP_LINK_STATUS_SIZE];
 546         int ret;
 547
 548         value = DP_TRAINING_PATTERN_2;
 549         writel(value, &regs->dp_training_ptn_set);
 550         ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
 551         if (ret)
 552                 return ret;
 553
 554         /* channel equalization loop */
 555         channel_eq = 0;
 556         for (tries = 0; tries < 5; tries++) {
 557                 rk_edp_set_link_training(edp, edp->train_set);
 558                 udelay(400);
 559
 560                 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
 561                         printf("displayport link status failed\n");
 562                         return -1;
 563                 }
 564
 565                 channel_eq = rk_edp_channel_eq(status,
 566                                                edp->link_train.lane_count);
 567                 if (!channel_eq)
 568                         break;
 569                 edp_get_adjust_train(status, edp->link_train.lane_count,
 570                                      edp->train_set);
 571         }
 572
 573         if (channel_eq) {
 574                 printf("channel eq failed, ret=%d\n", channel_eq);
 575                 return channel_eq;
 576         }
 577
 578         debug("channel eq at voltage %d pre-emphasis %d\n",
 579               edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 580               (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 581                         >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 582
 583         return 0;
 584 }
 585
 586 static int rk_edp_init_training(struct rk_edp_priv *edp)
 587 {
 588         u8 values[3];
 589         int ret;
 590
 591         ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
 592                                sizeof(values));
 593         if (ret < 0)
 594                 return ret;
 595
 596         edp->link_train.revision = values[0];
 597         edp->link_train.link_rate = values[1];
 598         edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
 599
 600         debug("max link rate:%d.%dGps max number of lanes:%d\n",
 601               edp->link_train.link_rate * 27 / 100,
 602               edp->link_train.link_rate * 27 % 100,
 603               edp->link_train.lane_count);
 604
 605         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 606             (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 607                 debug("Rx Max Link Rate is abnormal :%x\n",
 608                       edp->link_train.link_rate);
 609                 return -EPERM;
 610         }
 611
 612         if (edp->link_train.lane_count == 0) {
 613                 debug("Rx Max Lane count is abnormal :%x\n",
 614                       edp->link_train.lane_count);
 615                 return -EPERM;
 616         }
 617
 618         ret = rk_edp_link_power_up(edp);
 619         if (ret)
 620                 return ret;
 621
 622         return rk_edp_link_configure(edp);
 623 }
 624
 625 static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
 626 {
 627         ulong start;
 628         u32 val;
 629         int ret;
 630
 631         /* Set link rate and count as you want to establish */
 632         writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
 633         writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
 634
 635         ret = rk_edp_link_train_cr(edp);
 636         if (ret)
 637                 return ret;
 638         ret = rk_edp_link_train_ce(edp);
 639         if (ret)
 640                 return ret;
 641
 642         writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
 643         start = get_timer(0);
 644         do {
 645                 val = readl(&edp->regs->dp_hw_link_training);
 646                 if (!(val & HW_LT_EN))
 647                         break;
 648         } while (get_timer(start) < 10);
 649
 650         if (val & HW_LT_ERR_CODE_MASK) {
 651                 printf("edp hw link training error: %d\n",
 652                        val >> HW_LT_ERR_CODE_SHIFT);
 653                 return -EIO;
 654         }
 655
 656         return 0;
 657 }
 658
 659 static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
 660                                     unsigned int device_addr,
 661                                     unsigned int val_addr)
 662 {
 663         int ret;
 664
 665         /* Set EDID device address */
 666         writel(device_addr, &regs->aux_addr_7_0);
 667         writel(0x0, &regs->aux_addr_15_8);
 668         writel(0x0, &regs->aux_addr_19_16);
 669
 670         /* Set offset from base address of EDID device */
 671         writel(val_addr, &regs->buf_data[0]);
 672
 673         /*
 674          * Set I2C transaction and write address
 675          * If bit 3 is 1, DisplayPort transaction.
 676          * If Bit 3 is 0, I2C transaction.
 677          */
 678         writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 679                AUX_TX_COMM_WRITE, &regs->aux_ch_ctl_1);
 680
 681         /* Start AUX transaction */
 682         ret = rk_edp_start_aux_transaction(regs);
 683         if (ret != 0) {
 684                 debug("select_i2c_device Aux Transaction fail!\n");
 685                 return ret;
 686         }
 687
 688         return 0;
 689 }
 690
 691 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
 692                            unsigned int val_addr, unsigned int count, u8 edid[])
 693 {
 694         u32 val;
 695         unsigned int i, j;
 696         unsigned int cur_data_idx;
 697         unsigned int defer = 0;
 698         int ret = 0;
 699
 700         for (i = 0; i < count; i += 16) {
 701                 for (j = 0; j < 10; j++) { /* try 10 times */
 702                         /* Clear AUX CH data buffer */
 703                         writel(BUF_CLR, &regs->buf_data_ctl);
 704
 705                         /* Set normal AUX CH command */
 706                         clrbits_le32(&regs->aux_ch_ctl_2, ADDR_ONLY);
 707
 708                         /*
 709                          * If Rx sends defer, Tx sends only reads
 710                          * request without sending addres
 711                          */
 712                         if (!defer) {
 713                                 ret = rk_edp_select_i2c_device(regs,
 714                                                                device_addr,
 715                                                                val_addr + i);
 716                         } else {
 717                                 defer = 0;
 718                         }
 719
 720                         /*
 721                          * Set I2C transaction and write data
 722                          * If bit 3 is 1, DisplayPort transaction.
 723                          * If Bit 3 is 0, I2C transaction.
 724                          */
 725                         writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
 726                                AUX_TX_COMM_READ, &regs->aux_ch_ctl_1);
 727
 728                         /* Start AUX transaction */
 729                         ret = rk_edp_start_aux_transaction(regs);
 730                         if (ret == 0) {
 731                                 break;
 732                         } else {
 733                                 debug("Aux Transaction fail!\n");
 734                                 continue;
 735                         }
 736
 737                         /* Check if Rx sends defer */
 738                         val = readl(&regs->aux_rx_comm);
 739                         if (val == AUX_RX_COMM_AUX_DEFER ||
 740                             val == AUX_RX_COMM_I2C_DEFER) {
 741                                 debug("Defer: %d\n\n", val);
 742                                 defer = 1;
 743                         }
 744                 }
 745
 746                 if (ret)
 747                         return ret;
 748
 749                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 750                         val = readl(&regs->buf_data[cur_data_idx]);
 751                         edid[i + cur_data_idx] = (u8)val;
 752                 }
 753         }
 754
 755         return 0;
 756 }
 757
 758 static int rk_edp_set_link_train(struct rk_edp_priv *edp)
 759 {
 760         int ret;
 761
 762         ret = rk_edp_init_training(edp);
 763         if (ret) {
 764                 printf("DP LT init failed!\n");
 765                 return ret;
 766         }
 767
 768         ret = rk_edp_hw_link_training(edp);
 769         if (ret)
 770                 return ret;
 771
 772         return 0;
 773 }
 774
 775 static void rk_edp_init_video(struct rk3288_edp *regs)
 776 {
 777         writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
 778                &regs->common_int_sta_1);
 779         writel(CHA_CRI(4) | CHA_CTRL, &regs->sys_ctl_2);
 780         writel(VID_HRES_TH(2) | VID_VRES_TH(0), &regs->video_ctl_8);
 781 }
 782
 783 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
 784 {
 785         clrbits_le32(&regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
 786 }
 787
 788 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
 789                                    enum clock_recovery_m_value_type type,
 790                                    u32 m_value,
 791                                    u32 n_value)
 792 {
 793         if (type == REGISTER_M) {
 794                 setbits_le32(&regs->sys_ctl_4, FIX_M_VID);
 795                 writel(m_value & 0xff, &regs->m_vid_0);
 796                 writel((m_value >> 8) & 0xff, &regs->m_vid_1);
 797                 writel((m_value >> 16) & 0xff, &regs->m_vid_2);
 798
 799                 writel(n_value & 0xf, &regs->n_vid_0);
 800                 writel((n_value >> 8) & 0xff, &regs->n_vid_1);
 801                 writel((n_value >> 16) & 0xff, &regs->n_vid_2);
 802         } else {
 803                 clrbits_le32(&regs->sys_ctl_4, FIX_M_VID);
 804
 805                 writel(0x00, &regs->n_vid_0);
 806                 writel(0x80, &regs->n_vid_1);
 807                 writel(0x00, &regs->n_vid_2);
 808         }
 809 }
 810
 811 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
 812 {
 813         ulong start;
 814         u32 val;
 815
 816         start = get_timer(0);
 817         do {
 818                 val = readl(&regs->sys_ctl_1);
 819
 820                 /* must write value to update DET_STA bit status */
 821                 writel(val, &regs->sys_ctl_1);
 822                 val = readl(&regs->sys_ctl_1);
 823                 if (!(val & DET_STA))
 824                         continue;
 825
 826                 val = readl(&regs->sys_ctl_2);
 827
 828                 /* must write value to update CHA_STA bit status */
 829                 writel(val, &regs->sys_ctl_2);
 830                 val = readl(&regs->sys_ctl_2);
 831                 if (!(val & CHA_STA))
 832                         return 0;
 833
 834         } while (get_timer(start) < 100);
 835
 836         return -ETIMEDOUT;
 837 }
 838
 839 static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
 840 {
 841         ulong start;
 842         u32 val;
 843
 844         start = get_timer(0);
 845         do {
 846                 val = readl(&edp->regs->sys_ctl_3);
 847
 848                 /* must write value to update STRM_VALID bit status */
 849                 writel(val, &edp->regs->sys_ctl_3);
 850
 851                 val = readl(&edp->regs->sys_ctl_3);
 852                 if (!(val & STRM_VALID))
 853                         return 0;
 854         } while (get_timer(start) < 100);
 855
 856         return -ETIMEDOUT;
 857 }
 858
 859 static int rk_edp_config_video(struct rk_edp_priv *edp)
 860 {
 861         int ret;
 862
 863         rk_edp_config_video_slave_mode(edp->regs);
 864
 865         if (!rk_edp_get_pll_locked(edp->regs)) {
 866                 debug("PLL is not locked yet.\n");
 867                 return -ETIMEDOUT;
 868         }
 869
 870         ret = rk_edp_is_video_stream_clock_on(edp->regs);
 871         if (ret)
 872                 return ret;
 873
 874         /* Set to use the register calculated M/N video */
 875         rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
 876
 877         /* For video bist, Video timing must be generated by register */
 878         clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
 879
 880         /* Disable video mute */
 881         clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
 882
 883         /* Enable video at next frame */
 884         setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
 885
 886         return rk_edp_is_video_stream_on(edp);
 887 }
 888
 889 static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
 890 {
 891         setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
 892 }
 893
 894 static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
 895 {
 896         u32 val;
 897
 898         val = readl(&edp->regs->sys_ctl_3);
 899         if (val & HPD_STATUS)
 900                 return 1;
 901
 902         return 0;
 903 }
 904
 905 /*
 906  * support edp HPD function
 907  * some hardware version do not support edp hdp,
 908  * we use 200ms to try to get the hpd single now,
 909  * if we can not get edp hpd single, it will delay 200ms,
 910  * also meet the edp power timing request, to compatible
 911  * all of the hardware version
 912  */
 913 static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
 914 {
 915         ulong start;
 916
 917         start = get_timer(0);
 918         do {
 919                 if (rockchip_edp_get_plug_in_status(edp))
 920                         return;
 921                 udelay(100);
 922         } while (get_timer(start) < 200);
 923
 924         debug("do not get hpd single, force hpd\n");
 925         rockchip_edp_force_hpd(edp);
 926 }
 927
 928 static int rk_edp_enable(struct udevice *dev, int panel_bpp,
 929                          const struct display_timing *edid)
 930 {
 931         struct rk_edp_priv *priv = dev_get_priv(dev);
 932         int ret = 0;
 933
 934         ret = rk_edp_set_link_train(priv);
 935         if (ret) {
 936                 printf("link train failed!\n");
 937                 return ret;
 938         }
 939
 940         rk_edp_init_video(priv->regs);
 941         ret = rk_edp_config_video(priv);
 942         if (ret) {
 943                 printf("config video failed\n");
 944                 return ret;
 945         }
 946         ret = panel_enable_backlight(priv->panel);
 947         if (ret) {
 948                 debug("%s: backlight error: %d\n", __func__, ret);
 949                 return ret;
 950         }
 951
 952         return 0;
 953 }
 954
 955 static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 956 {
 957         struct rk_edp_priv *priv = dev_get_priv(dev);
 958         u32 edid_size = EDID_LENGTH;
 959         int ret;
 960         int i;
 961
 962         for (i = 0; i < 3; i++) {
 963                 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
 964                                       EDID_LENGTH, &buf[EDID_HEADER]);
 965                 if (ret) {
 966                         debug("EDID read failed\n");
 967                         continue;
 968                 }
 969
 970                 /*
 971                  * check if the EDID has an extension flag, and read additional
 972                  * EDID data if needed
 973                  */
 974                 if (buf[EDID_EXTENSION_FLAG]) {
 975                         edid_size += EDID_LENGTH;
 976                         ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
 977                                               EDID_LENGTH, EDID_LENGTH,
 978                                               &buf[EDID_LENGTH]);
 979                         if (ret) {
 980                                 debug("EDID Read failed!\n");
 981                                 continue;
 982                         }
 983                 }
 984                 goto done;
 985         }
 986
 987         /* After 3 attempts, give up */
 988         return ret;
 989
 990 done:
 991         return edid_size;
 992 }
 993
 994 static int rk_edp_ofdata_to_platdata(struct udevice *dev)
 995 {
 996         struct rk_edp_priv *priv = dev_get_priv(dev);
 997
 998         priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
 999         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1000
1001         return 0;
1002 }
1003
1004 static int rk_edp_remove(struct udevice *dev)
1005 {
1006         struct rk_edp_priv *priv = dev_get_priv(dev);
1007         struct rk3288_edp *regs = priv->regs;
1008
1009         setbits_le32(&regs->video_ctl_1, VIDEO_MUTE);
1010         clrbits_le32(&regs->video_ctl_1, VIDEO_EN);
1011         clrbits_le32(&regs->sys_ctl_3, F_HPD | HPD_CTRL);
1012         setbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
1013
1014         return 0;
1015 }
1016
1017 static int rk_edp_probe(struct udevice *dev)
1018 {
1019         struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
1020         struct rk_edp_priv *priv = dev_get_priv(dev);
1021         struct rk3288_edp *regs = priv->regs;
1022         struct clk clk;
1023         int ret;
1024
1025         ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1026                                            &priv->panel);
1027         if (ret) {
1028                 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1029                       dev->name, ret);
1030                 return ret;
1031         }
1032
1033         int vop_id = uc_plat->source_id;
1034         debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1035
1036         ret = clk_get_by_index(dev, 1, &clk);
1037         if (ret >= 0) {
1038                 ret = clk_set_rate(&clk, 0);
1039                 clk_free(&clk);
1040         }
1041         if (ret) {
1042                 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1043                 return ret;
1044         }
1045
1046         ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1047         if (ret >= 0) {
1048                 ret = clk_set_rate(&clk, 192000000);
1049                 clk_free(&clk);
1050         }
1051         if (ret < 0) {
1052                 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1053                       __func__, uc_plat->src_dev->name, ret);
1054                 return ret;
1055         }
1056
1057         /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1058         rk_setreg(&priv->grf->soc_con12, 1 << 4);
1059
1060         /* select epd signal from vop0 or vop1 */
1061         rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
1062
1063         rockchip_edp_wait_hpd(priv);
1064
1065         rk_edp_init_refclk(regs);
1066         rk_edp_init_interrupt(regs);
1067         rk_edp_enable_sw_function(regs);
1068         ret = rk_edp_init_analog_func(regs);
1069         if (ret)
1070                 return ret;
1071         rk_edp_init_aux(regs);
1072
1073         return 0;
1074 }
1075
1076 static const struct dm_display_ops dp_rockchip_ops = {
1077         .read_edid = rk_edp_read_edid,
1078         .enable = rk_edp_enable,
1079 };
1080
1081 static const struct udevice_id rockchip_dp_ids[] = {
1082         { .compatible = "rockchip,rk3288-edp" },
1083         { }
1084 };
1085
1086 U_BOOT_DRIVER(dp_rockchip) = {
1087         .name   = "edp_rockchip",
1088         .id     = UCLASS_DISPLAY,
1089         .of_match = rockchip_dp_ids,
1090         .ops    = &dp_rockchip_ops,
1091         .ofdata_to_platdata     = rk_edp_ofdata_to_platdata,
1092         .probe  = rk_edp_probe,
1093         .remove = rk_edp_remove,
1094         .priv_auto_alloc_size   = sizeof(struct rk_edp_priv),
1095 };