1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
4 * Copyright (c) 2015 Google, Inc
5 * Copyright 2014 Rockchip Inc.
17 #include <asm/hardware.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/hardware.h>
22 #include "rk_vop.h" /* for rk_vop_probe_regulators */
24 static const struct hdmi_phy_config rockchip_phy_config[] = {
26 .mpixelclock = 74250000,
27 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
29 .mpixelclock = 148500000,
30 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
32 .mpixelclock = 297000000,
33 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
35 .mpixelclock = 584000000,
36 .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
39 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
43 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
45 .mpixelclock = 40000000,
46 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
48 .mpixelclock = 65000000,
49 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
51 .mpixelclock = 66000000,
52 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
54 .mpixelclock = 83500000,
55 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
57 .mpixelclock = 146250000,
58 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
60 .mpixelclock = 148500000,
61 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
63 .mpixelclock = 272000000,
64 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
66 .mpixelclock = 340000000,
67 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
70 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
74 int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
76 struct rk_hdmi_priv *priv = dev_get_priv(dev);
78 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
81 int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
83 struct rk_hdmi_priv *priv = dev_get_priv(dev);
84 struct dw_hdmi *hdmi = &priv->hdmi;
86 hdmi->ioaddr = (ulong)dev_read_addr(dev);
87 hdmi->mpll_cfg = rockchip_mpll_cfg;
88 hdmi->phy_cfg = rockchip_phy_config;
90 /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
92 hdmi->reg_io_width = 4;
93 hdmi->phy_set = dw_hdmi_phy_cfg;
95 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
100 void rk_hdmi_probe_regulators(struct udevice *dev,
101 const char * const *names, int cnt)
103 rk_vop_probe_regulators(dev, names, cnt);
106 int rk_hdmi_probe(struct udevice *dev)
108 struct rk_hdmi_priv *priv = dev_get_priv(dev);
109 struct dw_hdmi *hdmi = &priv->hdmi;
112 ret = dw_hdmi_phy_wait_for_hpd(hdmi);
114 debug("hdmi can not get hpd signal\n");
119 dw_hdmi_phy_init(hdmi);