2 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
3 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
4 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
6 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/gpio.h>
17 #include <dm/device-internal.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 struct stm32_ltdc_priv {
23 struct display_timing timing;
24 enum video_log2_bpp l2bpp;
26 u32 crop_x, crop_y, crop_w, crop_h;
30 /* LTDC main registers */
31 #define LTDC_IDR 0x00 /* IDentification */
32 #define LTDC_LCR 0x04 /* Layer Count */
33 #define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
34 #define LTDC_BPCR 0x0C /* Back Porch Configuration */
35 #define LTDC_AWCR 0x10 /* Active Width Configuration */
36 #define LTDC_TWCR 0x14 /* Total Width Configuration */
37 #define LTDC_GCR 0x18 /* Global Control */
38 #define LTDC_GC1R 0x1C /* Global Configuration 1 */
39 #define LTDC_GC2R 0x20 /* Global Configuration 2 */
40 #define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
41 #define LTDC_GACR 0x28 /* GAmma Correction */
42 #define LTDC_BCCR 0x2C /* Background Color Configuration */
43 #define LTDC_IER 0x34 /* Interrupt Enable */
44 #define LTDC_ISR 0x38 /* Interrupt Status */
45 #define LTDC_ICR 0x3C /* Interrupt Clear */
46 #define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
47 #define LTDC_CPSR 0x44 /* Current Position Status */
48 #define LTDC_CDSR 0x48 /* Current Display Status */
50 /* LTDC layer 1 registers */
51 #define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */
52 #define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */
53 #define LTDC_L1CR 0x84 /* L1 Control */
54 #define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */
55 #define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */
56 #define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */
57 #define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */
58 #define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */
59 #define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */
60 #define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */
61 #define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */
62 #define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */
63 #define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */
64 #define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */
65 #define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */
66 #define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */
67 #define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */
68 #define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */
69 #define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */
72 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
73 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
75 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
76 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
78 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
79 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
81 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
82 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
84 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
85 #define GCR_DEN BIT(16) /* Dither ENable */
86 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
87 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
88 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
89 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
91 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
92 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
93 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
94 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
95 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
96 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
97 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
98 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
99 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
100 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
101 #define GC1R_TP BIT(25) /* Timing Programmable */
102 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
103 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
104 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
105 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
106 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
108 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
109 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
110 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
111 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
112 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
113 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
115 #define SRCR_IMR BIT(0) /* IMmediate Reload */
116 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
118 #define LXCR_LEN BIT(0) /* Layer ENable */
119 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
120 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
122 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
123 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
125 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
126 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
128 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
130 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
132 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
133 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
135 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
136 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
138 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
140 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
141 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
143 enum stm32_ltdc_pix_fmt {
154 /* TODO add more color format support */
155 static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
157 enum stm32_ltdc_pix_fmt pf;
170 debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
171 __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
176 debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
181 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
183 /* Reload configuration immediately & enable LTDC */
184 setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
185 setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
188 static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
190 void __iomem *regs = priv->regs;
191 struct display_timing *timing = &priv->timing;
192 u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
193 u32 total_w, total_h;
196 /* Convert video timings to ltdc timings */
197 hsync = timing->hsync_len.typ - 1;
198 vsync = timing->vsync_len.typ - 1;
199 acc_hbp = hsync + timing->hback_porch.typ;
200 acc_vbp = vsync + timing->vback_porch.typ;
201 acc_act_w = acc_hbp + timing->hactive.typ;
202 acc_act_h = acc_vbp + timing->vactive.typ;
203 total_w = acc_act_w + timing->hfront_porch.typ;
204 total_h = acc_act_h + timing->vfront_porch.typ;
206 /* Synchronization sizes */
207 val = (hsync << 16) | vsync;
208 clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
210 /* Accumulated back porch */
211 val = (acc_hbp << 16) | acc_vbp;
212 clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
214 /* Accumulated active width */
215 val = (acc_act_w << 16) | acc_act_h;
216 clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
218 /* Total width & height */
219 val = (total_w << 16) | total_h;
220 clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
222 setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
224 /* Signal polarities */
226 debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
227 if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
229 if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
231 if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
233 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
235 clrsetbits_le32(regs + LTDC_GCR,
236 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
238 /* Overall background color */
239 writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
242 static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
244 void __iomem *regs = priv->regs;
252 x1 = priv->crop_x + priv->crop_w - 1;
254 y1 = priv->crop_y + priv->crop_h - 1;
256 /* Horizontal start and stop position */
257 tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
258 val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
259 clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
262 /* Vertical start & stop position */
263 tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
264 val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
265 clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
268 /* Layer background color */
269 writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
271 /* Color frame buffer pitch in bytes & line length */
272 bpp = VNBITS(priv->l2bpp);
273 pitch_in_bytes = priv->crop_w * (bpp >> 3);
274 bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
275 line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
276 val = (pitch_in_bytes << 16) | line_length;
277 clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
280 val = stm32_ltdc_get_pixel_format(priv->l2bpp);
281 clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
283 /* Constant alpha value */
284 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
286 /* Blending factors */
287 clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
288 BF1_PAXCA | BF2_1PAXCA);
290 /* Frame buffer line number */
291 clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
293 /* Frame buffer address */
294 writel(fb_addr, regs + LTDC_L1CFBAR);
297 setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
300 static int stm32_ltdc_probe(struct udevice *dev)
302 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
303 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
304 struct stm32_ltdc_priv *priv = dev_get_priv(dev);
305 struct udevice *panel;
307 struct reset_ctl rst;
310 priv->regs = (void *)dev_read_addr(dev);
311 if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
312 debug("%s: ltdc dt register address error\n", __func__);
316 ret = clk_get_by_index(dev, 0, &pclk);
318 debug("%s: peripheral clock get error %d\n", __func__, ret);
322 ret = clk_enable(&pclk);
324 debug("%s: peripheral clock enable error %d\n",
329 ret = reset_get_by_index(dev, 0, &rst);
331 debug("%s: missing ltdc hardware reset\n", __func__);
336 reset_deassert(&rst);
338 ret = uclass_first_device(UCLASS_PANEL, &panel);
340 debug("%s: panel device error %d\n", __func__, ret);
344 ret = panel_enable_backlight(panel);
346 debug("%s: panel %s enable backlight error %d\n",
347 __func__, panel->name, ret);
351 ret = fdtdec_decode_display_timing(gd->fdt_blob,
352 dev_of_offset(dev), 0,
355 debug("%s: decode display timing error %d\n",
360 rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
362 debug("%s: fail to set pixel clock %d hz %d hz\n",
363 __func__, priv->timing.pixelclock.typ, rate);
367 debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
368 priv->timing.pixelclock.typ, rate);
370 /* TODO Below parameters are hard-coded for the moment... */
371 priv->l2bpp = VIDEO_BPP16;
372 priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
375 priv->crop_w = priv->timing.hactive.typ;
376 priv->crop_h = priv->timing.vactive.typ;
379 debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__,
380 priv->timing.hactive.typ, priv->timing.vactive.typ,
381 VNBITS(priv->l2bpp), uc_plat->base);
382 debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__,
383 priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
384 priv->bg_col_argb, priv->alpha);
386 /* Configure & start LTDC */
387 stm32_ltdc_set_mode(priv);
388 stm32_ltdc_set_layer1(priv, uc_plat->base);
389 stm32_ltdc_enable(priv);
391 uc_priv->xsize = priv->timing.hactive.typ;
392 uc_priv->ysize = priv->timing.vactive.typ;
393 uc_priv->bpix = priv->l2bpp;
395 video_set_flush_dcache(dev, true);
400 static int stm32_ltdc_bind(struct udevice *dev)
402 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
404 uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
405 CONFIG_VIDEO_STM32_MAX_YRES *
406 (CONFIG_VIDEO_STM32_MAX_BPP >> 3);
407 debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size);
412 static const struct udevice_id stm32_ltdc_ids[] = {
413 { .compatible = "st,stm32-ltdc" },
417 U_BOOT_DRIVER(stm32_ltdc) = {
418 .name = "stm32_display",
420 .of_match = stm32_ltdc_ids,
421 .probe = stm32_ltdc_probe,
422 .bind = stm32_ltdc_bind,
423 .priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),