git.sur5r.net Git - u-boot/blob - drivers/video/sunxi/sunxi_de2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Allwinner DE2 display driver
   4  *
   5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   6  */
   7
   8 #include <common.h>
   9 #include <display.h>
  10 #include <dm.h>
  11 #include <edid.h>
  12 #include <fdtdec.h>
  13 #include <fdt_support.h>
  14 #include <video.h>
  15 #include <asm/global_data.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/display2.h>
  19 #include <dm/device-internal.h>
  20 #include <dm/uclass-internal.h>
  21 #include "simplefb_common.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 enum {
  26         /* Maximum LCD size we support */
  27         LCD_MAX_WIDTH           = 3840,
  28         LCD_MAX_HEIGHT          = 2160,
  29         LCD_MAX_LOG2_BPP        = VIDEO_BPP32,
  30 };
  31
  32 static void sunxi_de2_composer_init(void)
  33 {
  34         struct sunxi_ccm_reg * const ccm =
  35                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  36
  37 #ifdef CONFIG_MACH_SUN50I
  38         u32 reg_value;
  39
  40         /* set SRAM for video use (A64 only) */
  41         reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
  42         reg_value &= ~(0x01 << 24);
  43         writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
  44 #endif
  45
  46         clock_set_pll10(432000000);
  47
  48         /* Set DE parent to pll10 */
  49         clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
  50                         CCM_DE2_CTRL_PLL10);
  51
  52         /* Set ahb gating to pass */
  53         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
  54         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
  55
  56         /* Clock on */
  57         setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
  58 }
  59
  60 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
  61                                int bpp, ulong address, bool is_composite)
  62 {
  63         ulong de_mux_base = (mux == 0) ?
  64                             SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
  65         struct de_clk * const de_clk_regs =
  66                 (struct de_clk *)(SUNXI_DE2_BASE);
  67         struct de_glb * const de_glb_regs =
  68                 (struct de_glb *)(de_mux_base +
  69                                   SUNXI_DE2_MUX_GLB_REGS);
  70         struct de_bld * const de_bld_regs =
  71                 (struct de_bld *)(de_mux_base +
  72                                   SUNXI_DE2_MUX_BLD_REGS);
  73         struct de_ui * const de_ui_regs =
  74                 (struct de_ui *)(de_mux_base +
  75                                  SUNXI_DE2_MUX_CHAN_REGS +
  76                                  SUNXI_DE2_MUX_CHAN_SZ * 1);
  77         struct de_csc * const de_csc_regs =
  78                 (struct de_csc *)(de_mux_base +
  79                                   SUNXI_DE2_MUX_DCSC_REGS);
  80         u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
  81         int channel;
  82         u32 format;
  83
  84         /* enable clock */
  85 #ifdef CONFIG_MACH_SUN8I_H3
  86         setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
  87 #else
  88         setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
  89 #endif
  90         setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
  91         setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
  92
  93         clrbits_le32(&de_clk_regs->sel_cfg, 1);
  94
  95         writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
  96         writel(0, &de_glb_regs->status);
  97         writel(1, &de_glb_regs->dbuff);
  98         writel(size, &de_glb_regs->size);
  99
 100         for (channel = 0; channel < 4; channel++) {
 101                 void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
 102                                     SUNXI_DE2_MUX_CHAN_SZ * channel);
 103                 memset(ch, 0, (channel == 0) ?
 104                         sizeof(struct de_vi) : sizeof(struct de_ui));
 105         }
 106         memset(de_bld_regs, 0, sizeof(struct de_bld));
 107
 108         writel(0x00000101, &de_bld_regs->fcolor_ctl);
 109
 110         writel(1, &de_bld_regs->route);
 111
 112         writel(0, &de_bld_regs->premultiply);
 113         writel(0xff000000, &de_bld_regs->bkcolor);
 114
 115         writel(0x03010301, &de_bld_regs->bld_mode[0]);
 116
 117         writel(size, &de_bld_regs->output_size);
 118         writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
 119                &de_bld_regs->out_ctl);
 120         writel(0, &de_bld_regs->ck_ctl);
 121
 122         writel(0xff000000, &de_bld_regs->attr[0].fcolor);
 123         writel(size, &de_bld_regs->attr[0].insize);
 124
 125         /* Disable all other units */
 126         writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
 127         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
 128         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
 129         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
 130         writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
 131         writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
 132         writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
 133         writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
 134         writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
 135         writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
 136
 137         if (is_composite) {
 138                 /* set CSC coefficients */
 139                 writel(0x107, &de_csc_regs->coef11);
 140                 writel(0x204, &de_csc_regs->coef12);
 141                 writel(0x64, &de_csc_regs->coef13);
 142                 writel(0x4200, &de_csc_regs->coef14);
 143                 writel(0x1f68, &de_csc_regs->coef21);
 144                 writel(0x1ed6, &de_csc_regs->coef22);
 145                 writel(0x1c2, &de_csc_regs->coef23);
 146                 writel(0x20200, &de_csc_regs->coef24);
 147                 writel(0x1c2, &de_csc_regs->coef31);
 148                 writel(0x1e87, &de_csc_regs->coef32);
 149                 writel(0x1fb7, &de_csc_regs->coef33);
 150                 writel(0x20200, &de_csc_regs->coef34);
 151
 152                 /* enable CSC unit */
 153                 writel(1, &de_csc_regs->csc_ctl);
 154         } else {
 155                 writel(0, &de_csc_regs->csc_ctl);
 156         }
 157
 158         switch (bpp) {
 159         case 16:
 160                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
 161                 break;
 162         case 32:
 163         default:
 164                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
 165                 break;
 166         }
 167
 168         writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
 169         writel(size, &de_ui_regs->cfg[0].size);
 170         writel(0, &de_ui_regs->cfg[0].coord);
 171         writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
 172         writel(address, &de_ui_regs->cfg[0].top_laddr);
 173         writel(size, &de_ui_regs->ovl_size);
 174
 175         /* apply settings */
 176         writel(1, &de_glb_regs->dbuff);
 177 }
 178
 179 static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
 180                           enum video_log2_bpp l2bpp,
 181                           struct udevice *disp, int mux, bool is_composite)
 182 {
 183         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 184         struct display_timing timing;
 185         struct display_plat *disp_uc_plat;
 186         int ret;
 187
 188         disp_uc_plat = dev_get_uclass_platdata(disp);
 189         debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
 190         if (display_in_use(disp)) {
 191                 debug("   - device in use\n");
 192                 return -EBUSY;
 193         }
 194
 195         disp_uc_plat->source_id = mux;
 196
 197         ret = device_probe(disp);
 198         if (ret) {
 199                 debug("%s: device '%s' display won't probe (ret=%d)\n",
 200                       __func__, dev->name, ret);
 201                 return ret;
 202         }
 203
 204         ret = display_read_timing(disp, &timing);
 205         if (ret) {
 206                 debug("%s: Failed to read timings\n", __func__);
 207                 return ret;
 208         }
 209
 210         sunxi_de2_composer_init();
 211         sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
 212
 213         ret = display_enable(disp, 1 << l2bpp, &timing);
 214         if (ret) {
 215                 debug("%s: Failed to enable display\n", __func__);
 216                 return ret;
 217         }
 218
 219         uc_priv->xsize = timing.hactive.typ;
 220         uc_priv->ysize = timing.vactive.typ;
 221         uc_priv->bpix = l2bpp;
 222         debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
 223
 224         return 0;
 225 }
 226
 227 static int sunxi_de2_probe(struct udevice *dev)
 228 {
 229         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 230         struct udevice *disp;
 231         int ret;
 232
 233         /* Before relocation we don't need to do anything */
 234         if (!(gd->flags & GD_FLG_RELOC))
 235                 return 0;
 236
 237         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 238                                          "sunxi_lcd", &disp);
 239         if (!ret) {
 240                 int mux;
 241
 242                 mux = 0;
 243
 244                 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
 245                                      false);
 246                 if (!ret) {
 247                         video_set_flush_dcache(dev, 1);
 248                         return 0;
 249                 }
 250         }
 251
 252         debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
 253
 254         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 255                                          "sunxi_dw_hdmi", &disp);
 256         if (!ret) {
 257                 int mux;
 258                 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
 259                         mux = 0;
 260                 else
 261                         mux = 1;
 262
 263                 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
 264                                      false);
 265                 if (!ret) {
 266                         video_set_flush_dcache(dev, 1);
 267                         return 0;
 268                 }
 269         }
 270
 271         debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
 272
 273         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 274                                         "sunxi_tve", &disp);
 275         if (ret) {
 276                 debug("%s: tv not found (ret=%d)\n", __func__, ret);
 277                 return ret;
 278         }
 279
 280         ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
 281         if (ret)
 282                 return ret;
 283
 284         video_set_flush_dcache(dev, 1);
 285
 286         return 0;
 287 }
 288
 289 static int sunxi_de2_bind(struct udevice *dev)
 290 {
 291         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 292
 293         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 294                 (1 << LCD_MAX_LOG2_BPP) / 8;
 295
 296         return 0;
 297 }
 298
 299 static const struct video_ops sunxi_de2_ops = {
 300 };
 301
 302 U_BOOT_DRIVER(sunxi_de2) = {
 303         .name   = "sunxi_de2",
 304         .id     = UCLASS_VIDEO,
 305         .ops    = &sunxi_de2_ops,
 306         .bind   = sunxi_de2_bind,
 307         .probe  = sunxi_de2_probe,
 308         .flags  = DM_FLAG_PRE_RELOC,
 309 };
 310
 311 U_BOOT_DEVICE(sunxi_de2) = {
 312         .name = "sunxi_de2"
 313 };
 314
 315 /*
 316  * Simplefb support.
 317  */
 318 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 319 int sunxi_simplefb_setup(void *blob)
 320 {
 321         struct udevice *de2, *hdmi, *lcd;
 322         struct video_priv *de2_priv;
 323         struct video_uc_platdata *de2_plat;
 324         int mux;
 325         int offset, ret;
 326         u64 start, size;
 327         const char *pipeline = NULL;
 328
 329         debug("Setting up simplefb\n");
 330
 331         if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
 332                 mux = 0;
 333         else
 334                 mux = 1;
 335
 336         /* Skip simplefb setting if DE2 / HDMI is not present */
 337         ret = uclass_find_device_by_name(UCLASS_VIDEO,
 338                                          "sunxi_de2", &de2);
 339         if (ret) {
 340                 debug("DE2 not present\n");
 341                 return 0;
 342         }
 343
 344         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 345                                          "sunxi_dw_hdmi", &hdmi);
 346         if (ret) {
 347                 debug("HDMI not present\n");
 348         } else if (device_active(hdmi)) {
 349                 if (mux == 0)
 350                         pipeline = "mixer0-lcd0-hdmi";
 351                 else
 352                         pipeline = "mixer1-lcd1-hdmi";
 353         } else {
 354                 debug("HDMI present but not probed\n");
 355         }
 356
 357         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 358                                          "sunxi_lcd", &lcd);
 359         if (ret)
 360                 debug("LCD not present\n");
 361         else if (device_active(lcd))
 362                 pipeline = "mixer0-lcd0";
 363         else
 364                 debug("LCD present but not probed\n");
 365
 366         if (!pipeline) {
 367                 debug("No active display present\n");
 368                 return 0;
 369         }
 370
 371         de2_priv = dev_get_uclass_priv(de2);
 372         de2_plat = dev_get_uclass_platdata(de2);
 373
 374         offset = sunxi_simplefb_fdt_match(blob, pipeline);
 375         if (offset < 0) {
 376                 eprintf("Cannot setup simplefb: node not found\n");
 377                 return 0; /* Keep older kernels working */
 378         }
 379
 380         start = gd->bd->bi_dram[0].start;
 381         size = de2_plat->base - start;
 382         ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
 383         if (ret) {
 384                 eprintf("Cannot setup simplefb: Error reserving memory\n");
 385                 return ret;
 386         }
 387
 388         ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base,
 389                         de2_priv->xsize, de2_priv->ysize,
 390                         VNBYTES(de2_priv->bpix) * de2_priv->xsize,
 391                         "x8r8g8b8");
 392         if (ret)
 393                 eprintf("Cannot setup simplefb: Error setting properties\n");
 394
 395         return ret;
 396 }
 397 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */