git.sur5r.net Git - u-boot/blob - drivers/video/sunxi/sunxi_de2.c

   1 /*
   2  * Allwinner DE2 display driver
   3  *
   4  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <edid.h>
  13 #include <video.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/display2.h>
  18 #include <dm/device-internal.h>
  19 #include <dm/uclass-internal.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 enum {
  24         /* Maximum LCD size we support */
  25         LCD_MAX_WIDTH           = 3840,
  26         LCD_MAX_HEIGHT          = 2160,
  27         LCD_MAX_LOG2_BPP        = VIDEO_BPP32,
  28 };
  29
  30 static void sunxi_de2_composer_init(void)
  31 {
  32         struct sunxi_ccm_reg * const ccm =
  33                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  34
  35 #ifdef CONFIG_MACH_SUN50I
  36         u32 reg_value;
  37
  38         /* set SRAM for video use (A64 only) */
  39         reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
  40         reg_value &= ~(0x01 << 24);
  41         writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
  42 #endif
  43
  44         clock_set_pll10(432000000);
  45
  46         /* Set DE parent to pll10 */
  47         clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
  48                         CCM_DE2_CTRL_PLL10);
  49
  50         /* Set ahb gating to pass */
  51         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
  52         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
  53
  54         /* Clock on */
  55         setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
  56 }
  57
  58 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
  59                                int bpp, ulong address, bool is_composite)
  60 {
  61         ulong de_mux_base = (mux == 0) ?
  62                             SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
  63         struct de_clk * const de_clk_regs =
  64                 (struct de_clk *)(SUNXI_DE2_BASE);
  65         struct de_glb * const de_glb_regs =
  66                 (struct de_glb *)(de_mux_base +
  67                                   SUNXI_DE2_MUX_GLB_REGS);
  68         struct de_bld * const de_bld_regs =
  69                 (struct de_bld *)(de_mux_base +
  70                                   SUNXI_DE2_MUX_BLD_REGS);
  71         struct de_ui * const de_ui_regs =
  72                 (struct de_ui *)(de_mux_base +
  73                                  SUNXI_DE2_MUX_CHAN_REGS +
  74                                  SUNXI_DE2_MUX_CHAN_SZ * 1);
  75         struct de_csc * const de_csc_regs =
  76                 (struct de_csc *)(de_mux_base +
  77                                   SUNXI_DE2_MUX_DCSC_REGS);
  78         u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
  79         int channel;
  80         u32 format;
  81
  82         /* enable clock */
  83 #ifdef CONFIG_MACH_SUN8I_H3
  84         setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
  85 #else
  86         setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
  87 #endif
  88         setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
  89         setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
  90
  91         clrbits_le32(&de_clk_regs->sel_cfg, 1);
  92
  93         writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
  94         writel(0, &de_glb_regs->status);
  95         writel(1, &de_glb_regs->dbuff);
  96         writel(size, &de_glb_regs->size);
  97
  98         for (channel = 0; channel < 4; channel++) {
  99                 void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
 100                                     SUNXI_DE2_MUX_CHAN_SZ * channel);
 101                 memset(ch, 0, (channel == 0) ?
 102                         sizeof(struct de_vi) : sizeof(struct de_ui));
 103         }
 104         memset(de_bld_regs, 0, sizeof(struct de_bld));
 105
 106         writel(0x00000101, &de_bld_regs->fcolor_ctl);
 107
 108         writel(1, &de_bld_regs->route);
 109
 110         writel(0, &de_bld_regs->premultiply);
 111         writel(0xff000000, &de_bld_regs->bkcolor);
 112
 113         writel(0x03010301, &de_bld_regs->bld_mode[0]);
 114
 115         writel(size, &de_bld_regs->output_size);
 116         writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
 117                &de_bld_regs->out_ctl);
 118         writel(0, &de_bld_regs->ck_ctl);
 119
 120         writel(0xff000000, &de_bld_regs->attr[0].fcolor);
 121         writel(size, &de_bld_regs->attr[0].insize);
 122
 123         /* Disable all other units */
 124         writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
 125         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
 126         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
 127         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
 128         writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
 129         writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
 130         writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
 131         writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
 132         writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
 133         writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
 134
 135         if (is_composite) {
 136                 /* set CSC coefficients */
 137                 writel(0x107, &de_csc_regs->coef11);
 138                 writel(0x204, &de_csc_regs->coef12);
 139                 writel(0x64, &de_csc_regs->coef13);
 140                 writel(0x4200, &de_csc_regs->coef14);
 141                 writel(0x1f68, &de_csc_regs->coef21);
 142                 writel(0x1ed6, &de_csc_regs->coef22);
 143                 writel(0x1c2, &de_csc_regs->coef23);
 144                 writel(0x20200, &de_csc_regs->coef24);
 145                 writel(0x1c2, &de_csc_regs->coef31);
 146                 writel(0x1e87, &de_csc_regs->coef32);
 147                 writel(0x1fb7, &de_csc_regs->coef33);
 148                 writel(0x20200, &de_csc_regs->coef34);
 149
 150                 /* enable CSC unit */
 151                 writel(1, &de_csc_regs->csc_ctl);
 152         } else {
 153                 writel(0, &de_csc_regs->csc_ctl);
 154         }
 155
 156         switch (bpp) {
 157         case 16:
 158                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
 159                 break;
 160         case 32:
 161         default:
 162                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
 163                 break;
 164         }
 165
 166         writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
 167         writel(size, &de_ui_regs->cfg[0].size);
 168         writel(0, &de_ui_regs->cfg[0].coord);
 169         writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
 170         writel(address, &de_ui_regs->cfg[0].top_laddr);
 171         writel(size, &de_ui_regs->ovl_size);
 172
 173         /* apply settings */
 174         writel(1, &de_glb_regs->dbuff);
 175 }
 176
 177 static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
 178                           enum video_log2_bpp l2bpp,
 179                           struct udevice *disp, int mux, bool is_composite)
 180 {
 181         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 182         struct display_timing timing;
 183         struct display_plat *disp_uc_plat;
 184         int ret;
 185
 186         disp_uc_plat = dev_get_uclass_platdata(disp);
 187         debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
 188         if (display_in_use(disp)) {
 189                 debug("   - device in use\n");
 190                 return -EBUSY;
 191         }
 192
 193         disp_uc_plat->source_id = mux;
 194
 195         ret = device_probe(disp);
 196         if (ret) {
 197                 debug("%s: device '%s' display won't probe (ret=%d)\n",
 198                       __func__, dev->name, ret);
 199                 return ret;
 200         }
 201
 202         ret = display_read_timing(disp, &timing);
 203         if (ret) {
 204                 debug("%s: Failed to read timings\n", __func__);
 205                 return ret;
 206         }
 207
 208         sunxi_de2_composer_init();
 209         sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
 210
 211         ret = display_enable(disp, 1 << l2bpp, &timing);
 212         if (ret) {
 213                 debug("%s: Failed to enable display\n", __func__);
 214                 return ret;
 215         }
 216
 217         uc_priv->xsize = timing.hactive.typ;
 218         uc_priv->ysize = timing.vactive.typ;
 219         uc_priv->bpix = l2bpp;
 220         debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
 221
 222         return 0;
 223 }
 224
 225 static int sunxi_de2_probe(struct udevice *dev)
 226 {
 227         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 228         struct udevice *disp;
 229         int ret;
 230
 231         /* Before relocation we don't need to do anything */
 232         if (!(gd->flags & GD_FLG_RELOC))
 233                 return 0;
 234
 235         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 236                                          "sunxi_dw_hdmi", &disp);
 237         if (!ret) {
 238                 int mux;
 239                 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
 240                         mux = 0;
 241                 else
 242                         mux = 1;
 243
 244                 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
 245                                      false);
 246                 if (!ret) {
 247                         video_set_flush_dcache(dev, 1);
 248                         return 0;
 249                 }
 250         }
 251
 252         debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
 253
 254         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 255                                         "sunxi_tve", &disp);
 256         if (ret) {
 257                 debug("%s: tv not found (ret=%d)\n", __func__, ret);
 258                 return ret;
 259         }
 260
 261         ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
 262         if (ret)
 263                 return ret;
 264
 265         video_set_flush_dcache(dev, 1);
 266
 267         return 0;
 268 }
 269
 270 static int sunxi_de2_bind(struct udevice *dev)
 271 {
 272         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 273
 274         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 275                 (1 << LCD_MAX_LOG2_BPP) / 8;
 276
 277         return 0;
 278 }
 279
 280 static const struct video_ops sunxi_de2_ops = {
 281 };
 282
 283 U_BOOT_DRIVER(sunxi_de2) = {
 284         .name   = "sunxi_de2",
 285         .id     = UCLASS_VIDEO,
 286         .ops    = &sunxi_de2_ops,
 287         .bind   = sunxi_de2_bind,
 288         .probe  = sunxi_de2_probe,
 289         .flags  = DM_FLAG_PRE_RELOC,
 290 };
 291
 292 U_BOOT_DEVICE(sunxi_de2) = {
 293         .name = "sunxi_de2"
 294 };