2 * Copyright (c) 2011-2013, NVIDIA Corporation.
3 * Copyright 2014 Google Inc.
5 * SPDX-License-Identifier: GPL-2.0
9 #include <displayport.h>
15 #include <asm/arch-tegra/dc.h>
16 #include "displayport.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 #define DO_FAST_LINK_TRAINING 1
24 struct tegra_dp_plat {
28 struct tegra_dp_priv {
29 struct dpaux_ctlr *regs;
30 struct tegra_dc_sor_data *sor;
35 struct tegra_dp_priv dp_data;
37 static inline u32 tegra_dpaux_readl(struct tegra_dp_priv *dp, u32 reg)
39 return readl((u32 *)dp->regs + reg);
42 static inline void tegra_dpaux_writel(struct tegra_dp_priv *dp, u32 reg,
45 writel(val, (u32 *)dp->regs + reg);
48 static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dp_priv *dp,
49 u32 reg, u32 mask, u32 exp_val,
54 u32 temp = timeout_us;
57 udelay(poll_interval_us);
58 reg_val = tegra_dpaux_readl(dp, reg);
59 if (timeout_us > poll_interval_us)
60 timeout_us -= poll_interval_us;
63 } while ((reg_val & mask) != exp_val);
65 if ((reg_val & mask) == exp_val)
66 return 0; /* success */
67 debug("dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
68 reg, reg_val, mask, exp_val);
72 static inline int tegra_dpaux_wait_transaction(struct tegra_dp_priv *dp)
74 /* According to DP spec, each aux transaction needs to finish
76 if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
77 DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
78 DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
79 100, DP_AUX_TIMEOUT_MS * 1000) != 0) {
80 debug("dp: DPAUX transaction timeout\n");
86 static int tegra_dc_dpaux_write_chunk(struct tegra_dp_priv *dp, u32 cmd,
87 u32 addr, u8 *data, u32 *size,
92 u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
93 u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
96 if (*size > DP_AUX_MAX_BYTES)
97 return -1; /* only write one chunk of data */
99 /* Make sure the command is write command */
101 case DPAUX_DP_AUXCTL_CMD_I2CWR:
102 case DPAUX_DP_AUXCTL_CMD_MOTWR:
103 case DPAUX_DP_AUXCTL_CMD_AUXWR:
106 debug("dp: aux write cmd 0x%x is invalid\n", cmd);
110 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
111 for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) {
112 memcpy(&temp_data, data, 4);
113 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data);
117 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
118 reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
120 reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
121 reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
123 while ((timeout_retries > 0) && (defer_retries > 0)) {
124 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
125 (defer_retries != DP_AUX_DEFER_MAX_TRIES))
128 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
129 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
131 if (tegra_dpaux_wait_transaction(dp))
132 debug("dp: aux write transaction timeout\n");
134 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
136 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
137 (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
138 (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
139 (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
140 if (timeout_retries-- > 0) {
141 debug("dp: aux write retry (0x%x) -- %d\n",
142 *aux_stat, timeout_retries);
143 /* clear the error bits */
144 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
148 debug("dp: aux write got error (0x%x)\n",
154 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
155 (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
156 if (defer_retries-- > 0) {
157 debug("dp: aux write defer (0x%x) -- %d\n",
158 *aux_stat, defer_retries);
159 /* clear the error bits */
160 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
164 debug("dp: aux write defer exceeds max retries (0x%x)\n",
170 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
171 DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
172 *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
175 debug("dp: aux write failed (0x%x)\n", *aux_stat);
179 /* Should never come to here */
183 static int tegra_dc_dpaux_read_chunk(struct tegra_dp_priv *dp, u32 cmd,
184 u32 addr, u8 *data, u32 *size,
188 u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
189 u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
191 if (*size > DP_AUX_MAX_BYTES) {
192 debug("only read one chunk\n");
193 return -EIO; /* only read one chunk */
196 /* Check to make sure the command is read command */
198 case DPAUX_DP_AUXCTL_CMD_I2CRD:
199 case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
200 case DPAUX_DP_AUXCTL_CMD_MOTRD:
201 case DPAUX_DP_AUXCTL_CMD_AUXRD:
204 debug("dp: aux read cmd 0x%x is invalid\n", cmd);
208 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
209 if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
210 debug("dp: HPD is not detected\n");
214 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
216 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
217 reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
219 reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
220 reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
221 while ((timeout_retries > 0) && (defer_retries > 0)) {
222 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
223 (defer_retries != DP_AUX_DEFER_MAX_TRIES))
224 udelay(DP_DPCP_RETRY_SLEEP_NS * 2);
226 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
227 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
229 if (tegra_dpaux_wait_transaction(dp))
230 debug("dp: aux read transaction timeout\n");
232 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
234 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
235 (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
236 (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
237 (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
238 if (timeout_retries-- > 0) {
239 debug("dp: aux read retry (0x%x) -- %d\n",
240 *aux_stat, timeout_retries);
241 /* clear the error bits */
242 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
244 continue; /* retry */
246 debug("dp: aux read got error (0x%x)\n",
252 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
253 (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
254 if (defer_retries-- > 0) {
255 debug("dp: aux read defer (0x%x) -- %d\n",
256 *aux_stat, defer_retries);
257 /* clear the error bits */
258 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
262 debug("dp: aux read defer exceeds max retries (0x%x)\n",
268 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
269 DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
273 for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i)
274 temp_data[i] = tegra_dpaux_readl(dp,
275 DPAUX_DP_AUXDATA_READ_W(i));
277 *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
278 memcpy(data, temp_data, *size);
282 debug("dp: aux read failed (0x%x\n", *aux_stat);
286 /* Should never come to here */
287 debug("%s: can't\n", __func__);
292 static int tegra_dc_dpaux_read(struct tegra_dp_priv *dp, u32 cmd, u32 addr,
293 u8 *data, u32 *size, u32 *aux_stat)
300 cur_size = *size - finished;
301 if (cur_size > DP_AUX_MAX_BYTES)
302 cur_size = DP_AUX_MAX_BYTES;
304 ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
305 data, &cur_size, aux_stat);
309 /* cur_size should be the real size returned */
312 finished += cur_size;
314 } while (*size > finished);
320 static int tegra_dc_dp_dpcd_read(struct tegra_dp_priv *dp, u32 cmd,
327 ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
328 cmd, data_ptr, &size, &status);
330 debug("dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
337 static int tegra_dc_dp_dpcd_write(struct tegra_dp_priv *dp, u32 cmd,
344 ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
345 cmd, &data, &size, &status);
347 debug("dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n",
354 static int tegra_dc_i2c_aux_read(struct tegra_dp_priv *dp, u32 i2c_addr,
355 u8 addr, u8 *data, u32 size, u32 *aux_stat)
361 u32 cur_size = min((u32)DP_AUX_MAX_BYTES, size - finished);
364 ret = tegra_dc_dpaux_write_chunk(
365 dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr,
366 &addr, &len, aux_stat);
368 debug("%s: error sending address to read.\n",
373 ret = tegra_dc_dpaux_read_chunk(
374 dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr,
375 data, &cur_size, aux_stat);
377 debug("%s: error reading data.\n", __func__);
381 /* cur_size should be the real size returned */
384 finished += cur_size;
385 } while (size > finished);
390 static void tegra_dc_dpaux_enable(struct tegra_dp_priv *dp)
392 /* clear interrupt */
393 tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
394 /* do not enable interrupt for now. Enable them when Isr in place */
395 tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
397 tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,
398 DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 |
399 DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 |
400 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT |
401 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
403 tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE,
404 DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP);
408 static void tegra_dc_dp_dump_link_cfg(struct tegra_dp_priv *dp,
409 const struct tegra_dp_link_config *link_cfg)
411 debug("DP config: cfg_name cfg_value\n");
412 debug(" Lane Count %d\n",
413 link_cfg->max_lane_count);
414 debug(" SupportEnhancedFraming %s\n",
415 link_cfg->support_enhanced_framing ? "Y" : "N");
416 debug(" Bandwidth %d\n",
417 link_cfg->max_link_bw);
419 link_cfg->bits_per_pixel);
420 debug(" EnhancedFraming %s\n",
421 link_cfg->enhanced_framing ? "Y" : "N");
422 debug(" Scramble_enabled %s\n",
423 link_cfg->scramble_ena ? "Y" : "N");
424 debug(" LinkBW %d\n",
426 debug(" lane_count %d\n",
427 link_cfg->lane_count);
428 debug(" activespolarity %d\n",
429 link_cfg->activepolarity);
430 debug(" active_count %d\n",
431 link_cfg->active_count);
432 debug(" tu_size %d\n",
434 debug(" active_frac %d\n",
435 link_cfg->active_frac);
436 debug(" watermark %d\n",
437 link_cfg->watermark);
438 debug(" hblank_sym %d\n",
439 link_cfg->hblank_sym);
440 debug(" vblank_sym %d\n",
441 link_cfg->vblank_sym);
445 static int _tegra_dp_lower_link_config(struct tegra_dp_priv *dp,
446 struct tegra_dp_link_config *cfg)
448 switch (cfg->link_bw) {
449 case SOR_LINK_SPEED_G1_62:
450 if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
451 cfg->link_bw = SOR_LINK_SPEED_G2_7;
452 cfg->lane_count /= 2;
454 case SOR_LINK_SPEED_G2_7:
455 cfg->link_bw = SOR_LINK_SPEED_G1_62;
457 case SOR_LINK_SPEED_G5_4:
458 if (cfg->lane_count == 1) {
459 cfg->link_bw = SOR_LINK_SPEED_G2_7;
460 cfg->lane_count = cfg->max_lane_count;
462 cfg->lane_count /= 2;
466 debug("dp: Error link rate %d\n", cfg->link_bw);
470 return (cfg->lane_count > 0) ? 0 : -ENOLINK;
474 * Calcuate if given cfg can meet the mode request.
475 * Return 0 if mode is possible, -1 otherwise
477 static int tegra_dc_dp_calc_config(struct tegra_dp_priv *dp,
478 const struct display_timing *timing,
479 struct tegra_dp_link_config *link_cfg)
481 const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000;
482 const u64 f = 100000; /* precision factor */
483 u32 num_linkclk_line; /* Number of link clocks per line */
484 u64 ratio_f; /* Ratio of incoming to outgoing data rate */
486 u64 activesym_f; /* Activesym per TU */
492 u64 accumulated_error_f = 0;
493 u32 lowest_neg_activecount = 0;
494 u32 lowest_neg_activepolarity = 0;
495 u32 lowest_neg_tusize = 64;
496 u32 num_symbols_per_line;
497 u64 lowest_neg_activefrac = 0;
498 u64 lowest_neg_error_f = 64 * f;
503 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ ||
504 !link_cfg->bits_per_pixel)
507 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >=
508 (u64)link_rate * 8 * link_cfg->lane_count)
511 num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ,
512 timing->pixelclock.typ));
514 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f;
516 do_div(ratio_f, link_rate * link_cfg->lane_count);
518 for (i = 64; i >= 32; --i) {
519 activesym_f = ratio_f * i;
520 activecount_f = lldiv(activesym_f, (u32)f) * f;
521 frac_f = activesym_f - activecount_f;
522 activecount = (u32)(lldiv(activecount_f, (u32)f));
524 if (frac_f < (lldiv(f, 2))) /* fraction < 0.5 */
532 /* warning: frac_f should be 64-bit */
533 frac_f = lldiv(f * f, frac_f); /* 1 / fraction */
534 if (frac_f > (15 * f))
535 activefrac = activepolarity ? 1 : 15;
537 activefrac = activepolarity ?
538 (u32)lldiv(frac_f, (u32)f) + 1 :
539 (u32)lldiv(frac_f, (u32)f);
545 if (activepolarity == 1)
546 approx_value_f = activefrac ? lldiv(
547 (activecount_f + (activefrac * f - f) * f),
551 approx_value_f = activefrac ?
552 activecount_f + lldiv(f, activefrac) :
555 if (activesym_f < approx_value_f) {
556 accumulated_error_f = num_linkclk_line *
557 lldiv(approx_value_f - activesym_f, i);
560 accumulated_error_f = num_linkclk_line *
561 lldiv(activesym_f - approx_value_f, i);
565 if ((neg && (lowest_neg_error_f > accumulated_error_f)) ||
566 (accumulated_error_f == 0)) {
567 lowest_neg_error_f = accumulated_error_f;
568 lowest_neg_tusize = i;
569 lowest_neg_activecount = activecount;
570 lowest_neg_activepolarity = activepolarity;
571 lowest_neg_activefrac = activefrac;
573 if (accumulated_error_f == 0)
578 if (lowest_neg_activefrac == 0) {
579 link_cfg->activepolarity = 0;
580 link_cfg->active_count = lowest_neg_activepolarity ?
581 lowest_neg_activecount : lowest_neg_activecount - 1;
582 link_cfg->tu_size = lowest_neg_tusize;
583 link_cfg->active_frac = 1;
585 link_cfg->activepolarity = lowest_neg_activepolarity;
586 link_cfg->active_count = (u32)lowest_neg_activecount;
587 link_cfg->tu_size = lowest_neg_tusize;
588 link_cfg->active_frac = (u32)lowest_neg_activefrac;
591 watermark_f = lldiv(ratio_f * link_cfg->tu_size * (f - ratio_f), f);
592 link_cfg->watermark = (u32)(lldiv(watermark_f + lowest_neg_error_f,
593 f)) + link_cfg->bits_per_pixel / 4 - 1;
594 num_symbols_per_line = (timing->hactive.typ *
595 link_cfg->bits_per_pixel) /
596 (8 * link_cfg->lane_count);
598 if (link_cfg->watermark > 30) {
599 debug("dp: sor setting: unable to get a good tusize, force watermark to 30\n");
600 link_cfg->watermark = 30;
602 } else if (link_cfg->watermark > num_symbols_per_line) {
603 debug("dp: sor setting: force watermark to the number of symbols in the line\n");
604 link_cfg->watermark = num_symbols_per_line;
609 * Refer to dev_disp.ref for more information.
610 * # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width -
611 * SetRasterBlankStart.X - 7) * link_clk / pclk)
612 * - 3 * enhanced_framing - Y
613 * where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12
615 link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ +
616 timing->hfront_porch.typ + timing->hsync_len.typ - 7) *
617 link_rate, timing->pixelclock.typ) -
618 3 * link_cfg->enhanced_framing -
619 (12 / link_cfg->lane_count);
621 if (link_cfg->hblank_sym < 0)
622 link_cfg->hblank_sym = 0;
626 * Refer to dev_disp.ref for more information.
627 * # symbols/vblank = ((SetRasterBlankStart.X -
628 * SetRasterBlankEen.X - 25) * link_clk / pclk)
630 * where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39
632 link_cfg->vblank_sym = (int)lldiv(((uint64_t)timing->hactive.typ - 25)
633 * link_rate, timing->pixelclock.typ) - (36 /
634 link_cfg->lane_count) - 4;
636 if (link_cfg->vblank_sym < 0)
637 link_cfg->vblank_sym = 0;
639 link_cfg->is_valid = 1;
641 tegra_dc_dp_dump_link_cfg(dp, link_cfg);
647 static int tegra_dc_dp_init_max_link_cfg(
648 const struct display_timing *timing,
649 struct tegra_dp_priv *dp,
650 struct tegra_dp_link_config *link_cfg)
652 const int drive_current = 0x40404040;
653 const int preemphasis = 0x0f0f0f0f;
654 const int postcursor = 0;
658 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data);
661 link_cfg->max_lane_count = dpcd_data & DP_MAX_LANE_COUNT_MASK;
662 link_cfg->tps3_supported = (dpcd_data &
663 DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0;
665 link_cfg->support_enhanced_framing =
666 (dpcd_data & DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
669 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data);
672 link_cfg->downspread = (dpcd_data & DP_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
675 ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL,
676 &link_cfg->aux_rd_interval);
679 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE,
680 &link_cfg->max_link_bw);
685 * Set to a high value for link training and attach.
686 * Will be re-programmed when dp is enabled.
688 link_cfg->drive_current = drive_current;
689 link_cfg->preemphasis = preemphasis;
690 link_cfg->postcursor = postcursor;
692 ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data);
696 link_cfg->alt_scramber_reset_cap =
697 (dpcd_data & DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES) ?
699 link_cfg->only_enhanced_framing =
700 (dpcd_data & DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES) ?
703 link_cfg->lane_count = link_cfg->max_lane_count;
704 link_cfg->link_bw = link_cfg->max_link_bw;
705 link_cfg->enhanced_framing = link_cfg->support_enhanced_framing;
706 link_cfg->frame_in_ms = (1000 / 60) + 1;
708 tegra_dc_dp_calc_config(dp, timing, link_cfg);
712 static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
713 struct tegra_dc_sor_data *sor, int ena)
718 DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE :
719 DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE;
721 ret = tegra_dc_dp_dpcd_write(dp, DP_EDP_CONFIGURATION_SET,
726 /* Also reset the scrambler to 0xfffe */
727 tegra_dc_sor_set_internal_panel(sor, ena);
731 static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp,
732 struct tegra_dc_sor_data *sor,
735 tegra_dc_sor_set_link_bandwidth(sor, link_bw);
738 return tegra_dc_dp_dpcd_write(dp, DP_LINK_BW_SET, link_bw);
741 static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp,
742 const struct tegra_dp_link_config *link_cfg,
743 struct tegra_dc_sor_data *sor)
748 /* check if panel support enhanched_framing */
749 dpcd_data = link_cfg->lane_count;
750 if (link_cfg->enhanced_framing)
751 dpcd_data |= DP_LANE_COUNT_SET_ENHANCEDFRAMING_T;
752 ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data);
756 tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
758 /* Also power down lanes that will not be used */
762 static int tegra_dc_dp_link_trained(struct tegra_dp_priv *dp,
763 const struct tegra_dp_link_config *cfg)
770 for (lane = 0; lane < cfg->lane_count; ++lane) {
771 ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ?
772 DP_LANE2_3_STATUS : DP_LANE0_1_STATUS,
777 NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
778 NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
779 NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
781 DP_LANE_CHANNEL_EQ_DONE |
782 DP_LANE_SYMBOL_LOCKED;
783 if ((data & mask) != mask)
789 static int tegra_dp_channel_eq_status(struct tegra_dp_priv *dp,
790 const struct tegra_dp_link_config *cfg)
793 u32 n_lanes = cfg->lane_count;
798 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
799 ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data);
804 ce_done = (data & (0x1 <<
805 NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) &&
807 NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT));
809 } else if (!(data & (0x1 <<
810 NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) ||
812 NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) ||
814 NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT)) ||
816 NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT)))
821 ret = tegra_dc_dp_dpcd_read(dp,
822 DP_LANE_ALIGN_STATUS_UPDATED,
826 if (!(data & NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES))
830 return ce_done ? 0 : -EIO;
833 static int tegra_dp_clock_recovery_status(struct tegra_dp_priv *dp,
834 const struct tegra_dp_link_config *cfg)
837 u32 n_lanes = cfg->lane_count;
841 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
842 ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt),
848 return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ?
850 else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ||
851 !(data_ptr & (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES)))
858 static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],
859 u32 pc[4], u8 pc_supported,
860 const struct tegra_dp_link_config *cfg)
864 u32 n_lanes = cfg->lane_count;
867 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
868 ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt,
872 pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>
873 NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT;
874 vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >>
875 NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT;
877 (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >>
878 NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT;
880 (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >>
881 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT;
884 ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2,
888 for (cnt = 0; cnt < n_lanes; cnt++) {
889 pc[cnt] = (data_ptr >>
890 NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt)) &
891 NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK;
898 static void tegra_dp_wait_aux_training(struct tegra_dp_priv *dp,
899 bool is_clk_recovery,
900 const struct tegra_dp_link_config *cfg)
902 if (!cfg->aux_rd_interval)
903 udelay(is_clk_recovery ? 200 : 500);
905 mdelay(cfg->aux_rd_interval * 4);
908 static void tegra_dp_tpg(struct tegra_dp_priv *dp, u32 tp, u32 n_lanes,
909 const struct tegra_dp_link_config *cfg)
911 u8 data = (tp == training_pattern_disabled)
912 ? (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F)
913 : (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T);
915 tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg);
916 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, data);
919 static int tegra_dp_link_config(struct tegra_dp_priv *dp,
920 const struct tegra_dp_link_config *link_cfg)
926 if (link_cfg->lane_count == 0) {
927 debug("dp: error: lane count is 0. Can not set link config.\n");
931 /* Set power state if it is not in normal level */
932 ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data);
936 if (dpcd_data == DP_SET_POWER_D3) {
937 dpcd_data = DP_SET_POWER_D0;
939 /* DP spec requires 3 retries */
940 for (retry = 3; retry > 0; --retry) {
941 ret = tegra_dc_dp_dpcd_write(dp, DP_SET_POWER,
946 debug("dp: Failed to set DP panel power\n");
952 /* Enable ASSR if possible */
953 if (link_cfg->alt_scramber_reset_cap) {
954 ret = tegra_dc_dp_set_assr(dp, dp->sor, 1);
959 ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw);
961 debug("dp: Failed to set link bandwidth\n");
964 ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor);
966 debug("dp: Failed to set lane count\n");
969 tegra_dc_sor_set_dp_linkctl(dp->sor, 1, training_pattern_none,
975 static int tegra_dp_lower_link_config(struct tegra_dp_priv *dp,
976 const struct display_timing *timing,
977 struct tegra_dp_link_config *cfg)
979 struct tegra_dp_link_config tmp_cfg;
985 ret = _tegra_dp_lower_link_config(dp, cfg);
987 ret = tegra_dc_dp_calc_config(dp, timing, cfg);
989 ret = tegra_dp_link_config(dp, cfg);
997 tegra_dp_link_config(dp, &tmp_cfg);
1001 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],
1002 u32 pc[4], const struct tegra_dp_link_config *cfg)
1004 struct tegra_dc_sor_data *sor = dp->sor;
1005 u32 n_lanes = cfg->lane_count;
1006 u8 pc_supported = cfg->tps3_supported;
1010 for (cnt = 0; cnt < n_lanes; cnt++) {
1012 u32 pe_reg, vs_reg, pc_reg;
1017 mask = PR_LANE2_DP_LANE0_MASK;
1018 shift = PR_LANE2_DP_LANE0_SHIFT;
1021 mask = PR_LANE1_DP_LANE1_MASK;
1022 shift = PR_LANE1_DP_LANE1_SHIFT;
1025 mask = PR_LANE0_DP_LANE2_MASK;
1026 shift = PR_LANE0_DP_LANE2_SHIFT;
1029 mask = PR_LANE3_DP_LANE3_MASK;
1030 shift = PR_LANE3_DP_LANE3_SHIFT;
1033 debug("dp: incorrect lane cnt\n");
1037 pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]];
1038 vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]];
1039 pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]];
1041 tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift,
1042 vs_reg << shift, pc_reg << shift,
1046 tegra_dp_disable_tx_pu(dp->sor);
1049 for (cnt = 0; cnt < n_lanes; cnt++) {
1050 u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]);
1051 u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]);
1053 val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) |
1055 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T :
1056 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F) |
1057 (pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |
1059 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T :
1060 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F);
1061 tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val);
1065 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
1066 u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]);
1067 u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]);
1068 val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) |
1070 NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T :
1071 NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F) |
1073 NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT) |
1075 NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T :
1076 NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F);
1077 tegra_dc_dp_dpcd_write(dp,
1078 NV_DPCD_TRAINING_LANE0_1_SET2 +
1086 static int _tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4],
1087 u32 vs[4], u32 pc[4], u8 pc_supported,
1089 const struct tegra_dp_link_config *cfg)
1093 for (retry_cnt = 0; retry_cnt < 4; retry_cnt++) {
1097 ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported,
1101 tegra_dp_lt_config(dp, pe, vs, pc, cfg);
1104 tegra_dp_wait_aux_training(dp, false, cfg);
1106 if (!tegra_dp_clock_recovery_status(dp, cfg)) {
1107 debug("dp: CR failed in channel EQ sequence!\n");
1111 if (!tegra_dp_channel_eq_status(dp, cfg))
1118 static int tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],
1120 const struct tegra_dp_link_config *cfg)
1122 u32 n_lanes = cfg->lane_count;
1123 u8 pc_supported = cfg->tps3_supported;
1125 u32 tp_src = training_pattern_2;
1128 tp_src = training_pattern_3;
1130 tegra_dp_tpg(dp, tp_src, n_lanes, cfg);
1132 ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg);
1134 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg);
1139 static int _tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4],
1140 u32 vs[4], u32 pc[4], u8 pc_supported,
1142 const struct tegra_dp_link_config *cfg)
1148 tegra_dp_lt_config(dp, pe, vs, pc, cfg);
1149 tegra_dp_wait_aux_training(dp, true, cfg);
1151 if (tegra_dp_clock_recovery_status(dp, cfg))
1154 memcpy(vs_temp, vs, sizeof(vs_temp));
1155 tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, cfg);
1157 if (memcmp(vs_temp, vs, sizeof(vs_temp)))
1161 } while (retry_cnt < 5);
1166 static int tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4],
1167 u32 vs[4], u32 pc[4],
1168 const struct tegra_dp_link_config *cfg)
1170 u32 n_lanes = cfg->lane_count;
1171 u8 pc_supported = cfg->tps3_supported;
1174 tegra_dp_tpg(dp, training_pattern_1, n_lanes, cfg);
1176 err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes,
1179 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg);
1184 static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp,
1185 const struct display_timing *timing,
1186 struct tegra_dp_link_config *cfg)
1188 struct tegra_dc_sor_data *sor = dp->sor;
1190 u32 pe[4], vs[4], pc[4];
1192 tegra_sor_precharge_lanes(sor, cfg);
1195 memset(pe, PREEMPHASIS_DISABLED, sizeof(pe));
1196 memset(vs, DRIVECURRENT_LEVEL0, sizeof(vs));
1197 memset(pc, POSTCURSOR2_LEVEL0, sizeof(pc));
1199 err = tegra_dp_clk_recovery(dp, pe, vs, pc, cfg);
1201 if (!tegra_dp_lower_link_config(dp, timing, cfg))
1204 debug("dp: clk recovery failed\n");
1208 err = tegra_dp_channel_eq(dp, pe, vs, pc, cfg);
1210 if (!tegra_dp_lower_link_config(dp, timing, cfg))
1213 debug("dp: channel equalization failed\n");
1217 tegra_dc_dp_dump_link_cfg(dp, cfg);
1226 * All link training functions are ported from kernel dc driver.
1227 * See more details at drivers/video/tegra/dc/dp.c
1229 static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp,
1230 const struct tegra_dp_link_config *link_cfg,
1231 struct tegra_dc_sor_data *sor)
1240 u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4);
1242 tegra_dc_sor_set_lane_parm(sor, link_cfg);
1243 tegra_dc_dp_dpcd_write(dp, DP_MAIN_LINK_CHANNEL_CODING_SET,
1247 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg);
1248 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET,
1249 DP_TRAINING_PATTERN_1);
1251 for (j = 0; j < link_cfg->lane_count; ++j)
1252 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24);
1255 size = sizeof(data16);
1256 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
1257 DP_LANE0_1_STATUS, (u8 *)&data16, &size, &status);
1258 status = mask & 0x1111;
1259 if ((data16 & status) != status) {
1260 debug("dp: Link training error for TP1 (%#x, status %#x)\n",
1266 tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena);
1267 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg);
1269 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET,
1270 link_cfg->link_bw == 20 ? 0x23 : 0x22);
1271 for (j = 0; j < link_cfg->lane_count; ++j)
1272 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24);
1275 size = sizeof(data32);
1276 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, DP_LANE0_1_STATUS,
1277 (u8 *)&data32, &size, &status);
1278 if ((data32 & mask) != (0x7777 & mask)) {
1279 debug("dp: Link training error for TP2/3 (0x%x)\n", data32);
1283 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled,
1285 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, 0);
1287 if (tegra_dc_dp_link_trained(dp, link_cfg)) {
1288 tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);
1289 debug("Fast link training failed, link bw %d, lane # %d\n",
1290 link_bw, lane_count);
1294 debug("Fast link training succeeded, link bw %d, lane %d\n",
1295 link_cfg->link_bw, link_cfg->lane_count);
1300 static int tegra_dp_do_link_training(struct tegra_dp_priv *dp,
1301 struct tegra_dp_link_config *link_cfg,
1302 const struct display_timing *timing,
1303 struct tegra_dc_sor_data *sor)
1309 if (DO_FAST_LINK_TRAINING) {
1310 ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor);
1312 debug("dp: fast link training failed\n");
1315 * set to a known-good drive setting if fast link
1316 * succeeded. Ignore any error.
1318 ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg);
1320 debug("Failed to set voltage swing\n");
1326 /* Try full link training then */
1327 ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg);
1329 debug("dp: full link training failed\n");
1334 /* Everything is good; double check the link config */
1335 tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);
1337 if ((link_cfg->link_bw == link_bw) &&
1338 (link_cfg->lane_count == lane_count))
1344 static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp,
1345 struct tegra_dp_link_config *link_cfg,
1346 struct tegra_dc_sor_data *sor,
1347 const struct display_timing *timing)
1349 struct tegra_dp_link_config temp_cfg;
1351 if (!timing->pixelclock.typ || !timing->hactive.typ ||
1352 !timing->vactive.typ) {
1353 debug("dp: error mode configuration");
1356 if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) {
1357 debug("dp: error link configuration");
1361 link_cfg->is_valid = 0;
1363 memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg));
1365 temp_cfg.link_bw = temp_cfg.max_link_bw;
1366 temp_cfg.lane_count = temp_cfg.max_lane_count;
1369 * set to max link config
1371 if ((!tegra_dc_dp_calc_config(dp, timing, &temp_cfg)) &&
1372 (!tegra_dp_link_config(dp, &temp_cfg)) &&
1373 (!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor)))
1374 /* the max link cfg is doable */
1375 memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg));
1377 return link_cfg->is_valid ? 0 : -EFAULT;
1380 static int tegra_dp_hpd_plug(struct tegra_dp_priv *dp)
1382 const int vdd_to_hpd_delay_ms = 200;
1386 start = get_timer(0);
1388 val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
1389 if (val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)
1392 } while (get_timer(start) < vdd_to_hpd_delay_ms);
1397 static int tegra_dc_dp_sink_out_of_sync(struct tegra_dp_priv *dp, u32 delay_ms)
1403 debug("%s: delay=%d\n", __func__, delay_ms);
1405 ret = tegra_dc_dp_dpcd_read(dp, DP_SINK_STATUS, &dpcd_data);
1409 out_of_sync = !(dpcd_data & DP_SINK_STATUS_PORT0_IN_SYNC);
1411 debug("SINK receive port 0 out of sync, data=%x\n", dpcd_data);
1413 debug("SINK is in synchronization\n");
1418 static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp,
1419 struct tegra_dp_link_config *link_cfg,
1420 const struct display_timing *timing)
1422 const int max_retry = 5;
1427 * DP TCON may skip some main stream frames, thus we need to wait
1428 * some delay before reading the DPCD SINK STATUS register, starting
1433 retries = max_retry;
1437 if (!tegra_dc_dp_sink_out_of_sync(dp, link_cfg->frame_in_ms *
1441 debug("%s: retries left %d\n", __func__, retries);
1443 printf("DP: Out of sync after %d retries\n", max_retry);
1446 ret = tegra_dc_sor_detach(dp->sor);
1449 if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,
1451 debug("dp: %s: error to configure link\n", __func__);
1455 tegra_dc_sor_set_power_state(dp->sor, 1);
1456 tegra_dc_sor_attach(dp->sor, link_cfg, timing);
1458 /* Increase delay_frame for next try in case the sink is
1459 skipping more frames */
1464 int tegra_dp_enable(struct udevice *dev, int panel_bpp,
1465 const struct display_timing *timing)
1467 struct tegra_dp_priv *priv = dev_get_priv(dev);
1468 struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg;
1469 struct tegra_dc_sor_data *sor;
1474 memset(link_cfg, '\0', sizeof(*link_cfg));
1475 link_cfg->is_valid = 0;
1476 link_cfg->scramble_ena = 1;
1478 tegra_dc_dpaux_enable(priv);
1480 if (tegra_dp_hpd_plug(priv) < 0) {
1481 debug("dp: hpd plug failed\n");
1485 link_cfg->bits_per_pixel = panel_bpp;
1486 if (tegra_dc_dp_init_max_link_cfg(timing, priv, link_cfg)) {
1487 debug("dp: failed to init link configuration\n");
1491 ret = tegra_dc_sor_init(&sor);
1495 ret = tegra_dc_sor_enable_dp(sor, link_cfg);
1499 tegra_dc_sor_set_panel_power(sor, 1);
1501 /* Write power on to DPCD */
1502 data = DP_SET_POWER_D0;
1505 ret = tegra_dc_dp_dpcd_write(priv, DP_SET_POWER, data);
1506 } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret);
1508 if (ret || retry >= DP_POWER_ON_MAX_TRIES) {
1509 debug("dp: failed to power on panel (0x%x)\n", ret);
1510 return -ENETUNREACH;
1514 /* Confirm DP plugging status */
1515 if (!(tegra_dpaux_readl(priv, DPAUX_DP_AUXSTAT) &
1516 DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
1517 debug("dp: could not detect HPD\n");
1521 /* Check DP version */
1522 if (tegra_dc_dp_dpcd_read(priv, DP_DPCD_REV, &priv->revision)) {
1523 debug("dp: failed to read the revision number from sink\n");
1527 if (tegra_dc_dp_explore_link_cfg(priv, link_cfg, sor, timing)) {
1528 debug("dp: error configuring link\n");
1532 tegra_dc_sor_set_power_state(sor, 1);
1533 ret = tegra_dc_sor_attach(sor, link_cfg, timing);
1534 if (ret && ret != -EEXIST)
1538 * This takes a long time, but can apparently resolve a failure to
1539 * bring up the display correctly.
1542 ret = tegra_dc_dp_check_sink(priv, link_cfg, timing);
1547 /* Power down the unused lanes to save power - a few hundred mW */
1548 tegra_dc_sor_power_down_unused_lanes(sor, link_cfg);
1550 priv->enabled = true;
1555 static int tegra_dp_ofdata_to_platdata(struct udevice *dev)
1557 struct tegra_dp_plat *plat = dev_get_platdata(dev);
1559 plat->base = dev_get_addr(dev);
1564 static int tegra_dp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
1566 struct tegra_dp_priv *priv = dev_get_priv(dev);
1567 const int tegra_edid_i2c_address = 0x50;
1570 tegra_dc_dpaux_enable(priv);
1572 return tegra_dc_i2c_aux_read(priv, tegra_edid_i2c_address, 0, buf,
1573 buf_size, &aux_stat);
1576 static const struct dm_display_port_ops dp_tegra_ops = {
1577 .read_edid = tegra_dp_read_edid,
1578 .enable = tegra_dp_enable,
1581 static int dp_tegra_probe(struct udevice *dev)
1583 struct tegra_dp_plat *plat = dev_get_platdata(dev);
1584 struct tegra_dp_priv *priv = dev_get_priv(dev);
1586 priv->regs = (struct dpaux_ctlr *)plat->base;
1587 priv->enabled = false;
1592 static const struct udevice_id tegra_dp_ids[] = {
1593 { .compatible = "nvidia,tegra124-dpaux" },
1597 U_BOOT_DRIVER(dp_tegra) = {
1598 .name = "dpaux_tegra",
1599 .id = UCLASS_DISPLAY_PORT,
1600 .of_match = tegra_dp_ids,
1601 .ofdata_to_platdata = tegra_dp_ofdata_to_platdata,
1602 .probe = dp_tegra_probe,
1603 .ops = &dp_tegra_ops,
1604 .priv_auto_alloc_size = sizeof(struct tegra_dp_priv),
1605 .platdata_auto_alloc_size = sizeof(struct tegra_dp_plat),