git.sur5r.net Git - u-boot/blob - drivers/video/tegra124/sor.c

   1 /*
   2  * Copyright (c) 2011-2013, NVIDIA Corporation.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch-tegra/dc.h>
  14 #include "displayport.h"
  15 #include "sor.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define DEBUG_SOR 0
  20
  21 #define APBDEV_PMC_DPD_SAMPLE                           0x20
  22 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE                0
  23 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE                 1
  24 #define APBDEV_PMC_SEL_DPD_TIM                          0x1c8
  25 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT      0x7f
  26 #define APBDEV_PMC_IO_DPD2_REQ                          0x1c0
  27 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT               25
  28 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF                 (0 << 25)
  29 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON                  (1 << 25)
  30 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT               30
  31 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK        (0x3 << 30)
  32 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE                (0 << 30)
  33 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF             (1 << 30)
  34 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON              (2 << 30)
  35 #define APBDEV_PMC_IO_DPD2_STATUS                       0x1c4
  36 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT            25
  37 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF              (0 << 25)
  38 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON               (1 << 25)
  39
  40 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
  41 {
  42         return readl((u32 *)sor->base + reg);
  43 }
  44
  45 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
  46                                     u32 val)
  47 {
  48         writel(val, (u32 *)sor->base + reg);
  49 }
  50
  51 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
  52         u32 reg, u32 mask, u32 val)
  53 {
  54         u32 reg_val = tegra_sor_readl(sor, reg);
  55         reg_val &= ~mask;
  56         reg_val |= val;
  57         tegra_sor_writel(sor, reg, reg_val);
  58 }
  59
  60 static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
  61                                       u32 mask, u32 exp_val,
  62                                       int poll_interval_us, int timeout_ms)
  63 {
  64         u32 reg_val = 0;
  65         ulong start;
  66
  67         start = get_timer(0);
  68         do {
  69                 reg_val = tegra_sor_readl(sor, reg);
  70                 if (((reg_val & mask) == exp_val))
  71                         return 0;
  72                 udelay(poll_interval_us);
  73         } while (get_timer(start) < timeout_ms);
  74
  75         debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
  76               reg, reg_val, mask, exp_val);
  77
  78         return -ETIMEDOUT;
  79 }
  80
  81 int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
  82 {
  83         u32 reg_val;
  84         u32 orig_val;
  85
  86         orig_val = tegra_sor_readl(sor, PWR);
  87
  88         reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
  89                 PWR_NORMAL_STATE_PD; /* normal state only */
  90
  91         if (reg_val == orig_val)
  92                 return 0;       /* No update needed */
  93
  94         reg_val |= PWR_SETTING_NEW_TRIGGER;
  95         tegra_sor_writel(sor, PWR, reg_val);
  96
  97         /* Poll to confirm it is done */
  98         if (tegra_dc_sor_poll_register(sor, PWR,
  99                                        PWR_SETTING_NEW_DEFAULT_MASK,
 100                                        PWR_SETTING_NEW_DONE,
 101                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 102                 debug("dc timeout waiting for SOR_PWR = NEW_DONE\n");
 103                 return -EFAULT;
 104         }
 105
 106         return 0;
 107 }
 108
 109 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
 110                                  u8 training_pattern,
 111                                  const struct tegra_dp_link_config *link_cfg)
 112 {
 113         u32 reg_val;
 114
 115         reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
 116
 117         if (ena)
 118                 reg_val |= DP_LINKCTL_ENABLE_YES;
 119         else
 120                 reg_val &= DP_LINKCTL_ENABLE_NO;
 121
 122         reg_val &= ~DP_LINKCTL_TUSIZE_MASK;
 123         reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);
 124
 125         if (link_cfg->enhanced_framing)
 126                 reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;
 127
 128         tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
 129
 130         switch (training_pattern) {
 131         case training_pattern_1:
 132                 tegra_sor_writel(sor, DP_TPG, 0x41414141);
 133                 break;
 134         case training_pattern_2:
 135         case training_pattern_3:
 136                 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
 137                         0x43434343 : 0x42424242;
 138                 tegra_sor_writel(sor, DP_TPG, reg_val);
 139                 break;
 140         default:
 141                 tegra_sor_writel(sor, DP_TPG, 0x50505050);
 142                 break;
 143         }
 144 }
 145
 146 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
 147                                               int pu, int is_lvds)
 148 {
 149         u32 reg_val;
 150
 151         /* SOR lane sequencer */
 152         if (pu) {
 153                 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 154                         LANE_SEQ_CTL_SEQUENCE_DOWN |
 155                         LANE_SEQ_CTL_NEW_POWER_STATE_PU;
 156         } else {
 157                 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 158                         LANE_SEQ_CTL_SEQUENCE_UP |
 159                         LANE_SEQ_CTL_NEW_POWER_STATE_PD;
 160         }
 161
 162         if (is_lvds)
 163                 reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;
 164         else
 165                 reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;
 166
 167         tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);
 168
 169         if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL,
 170                                        LANE_SEQ_CTL_SETTING_MASK,
 171                                        LANE_SEQ_CTL_SETTING_NEW_DONE,
 172                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 173                 debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n");
 174                 return -1;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
 181                                       u32 lane_count, int pu)
 182 {
 183         u32 reg_val;
 184
 185         reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
 186
 187         if (pu) {
 188                 switch (lane_count) {
 189                 case 4:
 190                         reg_val |= (DP_PADCTL_PD_TXD_3_NO |
 191                                 DP_PADCTL_PD_TXD_2_NO);
 192                         /* fall through */
 193                 case 2:
 194                         reg_val |= DP_PADCTL_PD_TXD_1_NO;
 195                 case 1:
 196                         reg_val |= DP_PADCTL_PD_TXD_0_NO;
 197                         break;
 198                 default:
 199                         debug("dp: invalid lane number %d\n", lane_count);
 200                         return -1;
 201                 }
 202
 203                 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
 204                 tegra_dc_sor_set_lane_count(sor, lane_count);
 205         }
 206
 207         return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
 208 }
 209
 210 void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
 211                                   int power_up)
 212 {
 213         u32 reg_val;
 214
 215         reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
 216
 217         if (power_up)
 218                 reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;
 219         else
 220                 reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;
 221
 222         tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
 223 }
 224
 225 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
 226                                     u32 pwm_dutycycle)
 227 {
 228         tegra_sor_writel(sor, PWM_DIV, pwm_div);
 229         tegra_sor_writel(sor, PWM_CTL,
 230                          (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) |
 231                          PWM_CTL_SETTING_NEW_TRIGGER);
 232
 233         if (tegra_dc_sor_poll_register(sor, PWM_CTL,
 234                                        PWM_CTL_SETTING_NEW_SHIFT,
 235                                        PWM_CTL_SETTING_NEW_DONE,
 236                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 237                 debug("dp: timeout while waiting for SOR PWM setting\n");
 238         }
 239 }
 240
 241 static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
 242                                 const struct tegra_dp_link_config *link_cfg)
 243 {
 244         u32 reg_val;
 245
 246         tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
 247
 248         tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
 249         reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
 250         reg_val &= ~DP_CONFIG_WATERMARK_MASK;
 251         reg_val |= link_cfg->watermark;
 252         reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;
 253         reg_val |= (link_cfg->active_count <<
 254                 DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
 255         reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;
 256         reg_val |= (link_cfg->active_frac <<
 257                 DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
 258         if (link_cfg->activepolarity)
 259                 reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 260         else
 261                 reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 262         reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
 263                 DP_CONFIG_RD_RESET_VAL_NEGATIVE);
 264
 265         tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);
 266
 267         /* program h/vblank sym */
 268         tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS,
 269                               DP_AUDIO_HBLANK_SYMBOLS_MASK,
 270                               link_cfg->hblank_sym);
 271
 272         tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS,
 273                               DP_AUDIO_VBLANK_SYMBOLS_MASK,
 274                               link_cfg->vblank_sym);
 275 }
 276
 277 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
 278 {
 279         tegra_sor_writel(sor, SUPER_STATE0, 0);
 280         tegra_sor_writel(sor, SUPER_STATE0, 1);
 281         tegra_sor_writel(sor, SUPER_STATE0, 0);
 282 }
 283
 284 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
 285 {
 286         tegra_sor_writel(sor, STATE0, 0);
 287         tegra_sor_writel(sor, STATE0, 1);
 288         tegra_sor_writel(sor, STATE0, 0);
 289 }
 290
 291 static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
 292 {
 293         u32 reg_val;
 294         void *pmc_base = sor->pmc_base;
 295
 296         if (up) {
 297                 writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
 298                        pmc_base + APBDEV_PMC_DPD_SAMPLE);
 299                 writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
 300         }
 301
 302         reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 303         reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
 304                         APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
 305
 306         reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
 307                         APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
 308                         APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
 309                         APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
 310
 311         writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 312
 313         /* Polling */
 314         u32 temp = 10 * 1000;
 315         do {
 316                 udelay(20);
 317                 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
 318                 if (temp > 20)
 319                         temp -= 20;
 320                 else
 321                         break;
 322         } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
 323
 324         if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {
 325                 debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
 326                 return -EIO;
 327         }
 328
 329         if (up) {
 330                 writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
 331                        pmc_base + APBDEV_PMC_DPD_SAMPLE);
 332         }
 333
 334         return 0;
 335 }
 336
 337 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
 338 {
 339         u32 reg_val;
 340
 341         reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
 342         if (is_int)
 343                 reg_val |= DP_SPARE_PANEL_INTERNAL;
 344         else
 345                 reg_val &= ~DP_SPARE_PANEL_INTERNAL;
 346
 347         reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
 348                 DP_SPARE_SEQ_ENABLE_YES;
 349         tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
 350 }
 351
 352 void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
 353                                    u8 *lane_count)
 354 {
 355         u32 reg_val;
 356
 357         reg_val = tegra_sor_readl(sor, CLK_CNTRL);
 358         *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)
 359                 >> CLK_CNTRL_DP_LINK_SPEED_SHIFT;
 360         reg_val = tegra_sor_readl(sor,
 361                 DP_LINKCTL(sor->portnum));
 362
 363         switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {
 364         case DP_LINKCTL_LANECOUNT_ZERO:
 365                 *lane_count = 0;
 366                 break;
 367         case DP_LINKCTL_LANECOUNT_ONE:
 368                 *lane_count = 1;
 369                 break;
 370         case DP_LINKCTL_LANECOUNT_TWO:
 371                 *lane_count = 2;
 372                 break;
 373         case DP_LINKCTL_LANECOUNT_FOUR:
 374                 *lane_count = 4;
 375                 break;
 376         default:
 377                 printf("Unknown lane count\n");
 378         }
 379 }
 380
 381 void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
 382 {
 383         tegra_sor_write_field(sor, CLK_CNTRL,
 384                               CLK_CNTRL_DP_LINK_SPEED_MASK,
 385                               link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
 386 }
 387
 388 void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
 389 {
 390         u32 reg_val;
 391
 392         reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
 393         reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;
 394         switch (lane_count) {
 395         case 0:
 396                 break;
 397         case 1:
 398                 reg_val |= DP_LINKCTL_LANECOUNT_ONE;
 399                 break;
 400         case 2:
 401                 reg_val |= DP_LINKCTL_LANECOUNT_TWO;
 402                 break;
 403         case 4:
 404                 reg_val |= DP_LINKCTL_LANECOUNT_FOUR;
 405                 break;
 406         default:
 407                 /* 0 should be handled earlier. */
 408                 printf("dp: Invalid lane count %d\n", lane_count);
 409                 return;
 410         }
 411         tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
 412 }
 413
 414 /*
 415  * The SOR power sequencer does not work for t124 so SW has to
 416  *  go through the power sequence manually
 417  * Power up steps from spec:
 418  * STEP PDPORT  PDPLL   PDBG    PLLVCOD PLLCAPD E_DPD   PDCAL
 419  * 1    1       1       1       1       1       1       1
 420  * 2    1       1       1       1       1       0       1
 421  * 3    1       1       0       1       1       0       1
 422  * 4    1       0       0       0       0       0       1
 423  * 5    0       0       0       0       0       0       1
 424  */
 425 static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds)
 426 {
 427         int ret;
 428
 429         if (sor->power_is_up)
 430                 return 0;
 431
 432         /* Set link bw */
 433         tegra_dc_sor_set_link_bandwidth(sor, is_lvds ?
 434                                         CLK_CNTRL_DP_LINK_SPEED_LVDS :
 435                                         CLK_CNTRL_DP_LINK_SPEED_G1_62);
 436
 437         /* step 1 */
 438         tegra_sor_write_field(sor, PLL2,
 439                               PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
 440                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
 441                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
 442                               PLL2_AUX7_PORT_POWERDOWN_ENABLE |
 443                               PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
 444                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
 445         tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
 446                               PLL0_VCOPD_MASK, /* PLLVCOPD */
 447                               PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
 448         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 449                               DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
 450                               DP_PADCTL_PAD_CAL_PD_POWERDOWN);
 451
 452         /* step 2 */
 453         ret = tegra_dc_sor_io_set_dpd(sor, 1);
 454         if (ret)
 455                 return ret;
 456         udelay(15);
 457
 458         /* step 3 */
 459         tegra_sor_write_field(sor, PLL2,
 460                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 461                               PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 462         udelay(25);
 463
 464         /* step 4 */
 465         tegra_sor_write_field(sor, PLL0,
 466                               PLL0_PWR_MASK | /* PDPLL */
 467                               PLL0_VCOPD_MASK, /* PLLVCOPD */
 468                               PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
 469         /* PLLCAPD */
 470         tegra_sor_write_field(sor, PLL2,
 471                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 472                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 473         udelay(225);
 474
 475         /* step 5 PDPORT */
 476         tegra_sor_write_field(sor, PLL2,
 477                               PLL2_AUX7_PORT_POWERDOWN_MASK,
 478                               PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 479
 480         sor->power_is_up = 1;
 481
 482         return 0;
 483 }
 484
 485 #if DEBUG_SOR
 486 static void dump_sor_reg(struct tegra_dc_sor_data *sor)
 487 {
 488 #define DUMP_REG(a) printk(BIOS_INFO, "%-32s  %03x  %08x\n",            \
 489                 #a, a, tegra_sor_readl(sor, a));
 490
 491         DUMP_REG(SUPER_STATE0);
 492         DUMP_REG(SUPER_STATE1);
 493         DUMP_REG(STATE0);
 494         DUMP_REG(STATE1);
 495         DUMP_REG(NV_HEAD_STATE0(0));
 496         DUMP_REG(NV_HEAD_STATE0(1));
 497         DUMP_REG(NV_HEAD_STATE1(0));
 498         DUMP_REG(NV_HEAD_STATE1(1));
 499         DUMP_REG(NV_HEAD_STATE2(0));
 500         DUMP_REG(NV_HEAD_STATE2(1));
 501         DUMP_REG(NV_HEAD_STATE3(0));
 502         DUMP_REG(NV_HEAD_STATE3(1));
 503         DUMP_REG(NV_HEAD_STATE4(0));
 504         DUMP_REG(NV_HEAD_STATE4(1));
 505         DUMP_REG(NV_HEAD_STATE5(0));
 506         DUMP_REG(NV_HEAD_STATE5(1));
 507         DUMP_REG(CRC_CNTRL);
 508         DUMP_REG(CLK_CNTRL);
 509         DUMP_REG(CAP);
 510         DUMP_REG(PWR);
 511         DUMP_REG(TEST);
 512         DUMP_REG(PLL0);
 513         DUMP_REG(PLL1);
 514         DUMP_REG(PLL2);
 515         DUMP_REG(PLL3);
 516         DUMP_REG(CSTM);
 517         DUMP_REG(LVDS);
 518         DUMP_REG(CRCA);
 519         DUMP_REG(CRCB);
 520         DUMP_REG(SEQ_CTL);
 521         DUMP_REG(LANE_SEQ_CTL);
 522         DUMP_REG(SEQ_INST(0));
 523         DUMP_REG(SEQ_INST(1));
 524         DUMP_REG(SEQ_INST(2));
 525         DUMP_REG(SEQ_INST(3));
 526         DUMP_REG(SEQ_INST(4));
 527         DUMP_REG(SEQ_INST(5));
 528         DUMP_REG(SEQ_INST(6));
 529         DUMP_REG(SEQ_INST(7));
 530         DUMP_REG(SEQ_INST(8));
 531         DUMP_REG(PWM_DIV);
 532         DUMP_REG(PWM_CTL);
 533         DUMP_REG(MSCHECK);
 534         DUMP_REG(XBAR_CTRL);
 535         DUMP_REG(DP_LINKCTL(0));
 536         DUMP_REG(DP_LINKCTL(1));
 537         DUMP_REG(DC(0));
 538         DUMP_REG(DC(1));
 539         DUMP_REG(LANE_DRIVE_CURRENT(0));
 540         DUMP_REG(PR(0));
 541         DUMP_REG(LANE4_PREEMPHASIS(0));
 542         DUMP_REG(POSTCURSOR(0));
 543         DUMP_REG(DP_CONFIG(0));
 544         DUMP_REG(DP_CONFIG(1));
 545         DUMP_REG(DP_MN(0));
 546         DUMP_REG(DP_MN(1));
 547         DUMP_REG(DP_PADCTL(0));
 548         DUMP_REG(DP_PADCTL(1));
 549         DUMP_REG(DP_DEBUG(0));
 550         DUMP_REG(DP_DEBUG(1));
 551         DUMP_REG(DP_SPARE(0));
 552         DUMP_REG(DP_SPARE(1));
 553         DUMP_REG(DP_TPG);
 554
 555         return;
 556 }
 557 #endif
 558
 559 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
 560                         int is_lvds,
 561                         const struct tegra_dp_link_config *link_cfg,
 562                         const struct display_timing *timing)
 563 {
 564         const int       head_num = 0;
 565         u32             reg_val  = STATE1_ASY_OWNER_HEAD0 << head_num;
 566         u32             vtotal, htotal;
 567         u32             vsync_end, hsync_end;
 568         u32             vblank_end, hblank_end;
 569         u32             vblank_start, hblank_start;
 570
 571         reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
 572                 STATE1_ASY_PROTOCOL_DP_A;
 573         reg_val |= STATE1_ASY_SUBOWNER_NONE |
 574                 STATE1_ASY_CRCMODE_COMPLETE_RASTER;
 575
 576         reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
 577         reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
 578         reg_val |= (link_cfg->bits_per_pixel > 18) ?
 579                 STATE1_ASY_PIXELDEPTH_BPP_24_444 :
 580                 STATE1_ASY_PIXELDEPTH_BPP_18_444;
 581
 582         tegra_sor_writel(sor, STATE1, reg_val);
 583
 584         /*
 585          * Skipping programming NV_HEAD_STATE0, assuming:
 586          * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
 587          */
 588         vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
 589                 timing->vactive.typ + timing->vfront_porch.typ;
 590         htotal = timing->hsync_len.typ + timing->hback_porch.typ +
 591                 timing->hactive.typ + timing->hfront_porch.typ;
 592
 593         tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
 594                          vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
 595                          htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
 596
 597         vsync_end = timing->vsync_len.typ - 1;
 598         hsync_end = timing->hsync_len.typ - 1;
 599         tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
 600                          vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
 601                          hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
 602
 603         vblank_end = vsync_end + timing->vback_porch.typ;
 604         hblank_end = hsync_end + timing->hback_porch.typ;
 605         tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
 606                          vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
 607                          hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
 608
 609         vblank_start = vblank_end + timing->vactive.typ;
 610         hblank_start = hblank_end + timing->hactive.typ;
 611         tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
 612                          vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
 613                          hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
 614
 615         /* TODO: adding interlace mode support */
 616         tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
 617
 618         tegra_sor_write_field(sor, CSTM,
 619                               CSTM_ROTCLK_DEFAULT_MASK |
 620                               CSTM_LVDS_EN_ENABLE,
 621                               2 << CSTM_ROTCLK_SHIFT |
 622                               is_lvds ? CSTM_LVDS_EN_ENABLE :
 623                               CSTM_LVDS_EN_DISABLE);
 624
 625          tegra_dc_sor_config_pwm(sor, 1024, 1024);
 626 }
 627
 628 static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
 629 {
 630         u32 reg_val = readl(&disp_ctrl->cmd.state_access);
 631
 632         writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 633         writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
 634
 635         /* Enable DC now - otherwise pure text console may not show. */
 636         writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
 637                &disp_ctrl->cmd.disp_cmd);
 638         writel(reg_val, &disp_ctrl->cmd.state_access);
 639 }
 640
 641 int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
 642                            const struct tegra_dp_link_config *link_cfg)
 643 {
 644         int ret;
 645
 646         tegra_sor_write_field(sor, CLK_CNTRL,
 647                               CLK_CNTRL_DP_CLK_SEL_MASK,
 648                               CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
 649
 650         tegra_sor_write_field(sor, PLL2,
 651                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 652                               PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 653         udelay(25);
 654
 655         tegra_sor_write_field(sor, PLL3,
 656                               PLL3_PLLVDD_MODE_MASK,
 657                               PLL3_PLLVDD_MODE_V3_3);
 658         tegra_sor_writel(sor, PLL0,
 659                          0xf << PLL0_ICHPMP_SHFIT |
 660                          0x3 << PLL0_VCOCAP_SHIFT |
 661                          PLL0_PLLREG_LEVEL_V45 |
 662                          PLL0_RESISTORSEL_EXT |
 663                          PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
 664         tegra_sor_write_field(sor, PLL2,
 665                               PLL2_AUX1_SEQ_MASK |
 666                               PLL2_AUX9_LVDSEN_OVERRIDE |
 667                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 668                               PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
 669                               PLL2_AUX9_LVDSEN_OVERRIDE |
 670                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 671         tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
 672                          PLL1_TMDS_TERM_ENABLE);
 673
 674         if (tegra_dc_sor_poll_register(sor, PLL2,
 675                                        PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 676                                        PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
 677                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 678                 printf("DP failed to lock PLL\n");
 679                 return -EIO;
 680         }
 681
 682         tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
 683                               PLL2_AUX7_PORT_POWERDOWN_MASK,
 684                               PLL2_AUX2_OVERRIDE_POWERDOWN |
 685                               PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 686
 687         ret = tegra_dc_sor_power_up(sor, 0);
 688         if (ret) {
 689                 debug("DP failed to power up\n");
 690                 return ret;
 691         }
 692
 693         /* re-enable SOR clock */
 694         clock_sor_enable_edp_clock();
 695
 696         /* Power up lanes */
 697         tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
 698
 699         tegra_dc_sor_set_dp_mode(sor, link_cfg);
 700         debug("%s ret\n", __func__);
 701
 702         return 0;
 703 }
 704
 705 int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
 706                         const struct tegra_dp_link_config *link_cfg,
 707                         const struct display_timing *timing)
 708 {
 709         const void *blob = gd->fdt_blob;
 710         struct dc_ctlr *disp_ctrl;
 711         u32 reg_val;
 712         int node;
 713
 714         /* Use the first display controller */
 715         debug("%s\n", __func__);
 716         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
 717         if (node < 0)
 718                 return -ENOENT;
 719         disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
 720
 721         tegra_dc_sor_enable_dc(disp_ctrl);
 722         tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
 723
 724         writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
 725         writel(0x9f, &disp_ctrl->cmd.state_ctrl);
 726
 727         writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 728                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
 729                &disp_ctrl->cmd.disp_pow_ctrl);
 730
 731         reg_val = tegra_sor_readl(sor, TEST);
 732         if (reg_val & TEST_ATTACHED_TRUE)
 733                 return -EEXIST;
 734
 735         tegra_sor_writel(sor, SUPER_STATE1,
 736                          SUPER_STATE1_ATTACHED_NO);
 737
 738         /*
 739          * Enable display2sor clock at least 2 cycles before DC start,
 740          * to clear sor internal valid signal.
 741          */
 742         writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
 743         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 744         writel(0, &disp_ctrl->disp.disp_win_opt);
 745         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 746
 747         /* Attach head */
 748         tegra_dc_sor_update(sor);
 749         tegra_sor_writel(sor, SUPER_STATE1,
 750                          SUPER_STATE1_ATTACHED_YES);
 751         tegra_sor_writel(sor, SUPER_STATE1,
 752                          SUPER_STATE1_ATTACHED_YES |
 753                          SUPER_STATE1_ASY_HEAD_OP_AWAKE |
 754                          SUPER_STATE1_ASY_ORMODE_NORMAL);
 755         tegra_dc_sor_super_update(sor);
 756
 757         /* Enable dc */
 758         reg_val = readl(&disp_ctrl->cmd.state_access);
 759         writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 760         writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
 761                &disp_ctrl->cmd.disp_cmd);
 762         writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
 763         writel(reg_val, &disp_ctrl->cmd.state_access);
 764
 765         if (tegra_dc_sor_poll_register(sor, TEST,
 766                                        TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
 767                                        TEST_ACT_HEAD_OPMODE_AWAKE,
 768                                        100,
 769                                        TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
 770                 printf("dc timeout waiting for OPMOD = AWAKE\n");
 771                 return -ETIMEDOUT;
 772         } else {
 773                 debug("%s: sor is attached\n", __func__);
 774         }
 775
 776 #if DEBUG_SOR
 777         dump_sor_reg(sor);
 778 #endif
 779         debug("%s: ret=%d\n", __func__, 0);
 780
 781         return 0;
 782 }
 783
 784 void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
 785                 const struct tegra_dp_link_config *link_cfg)
 786 {
 787         tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
 788                          link_cfg->drive_current);
 789         tegra_sor_writel(sor, PR(sor->portnum),
 790                          link_cfg->preemphasis);
 791         tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
 792                          link_cfg->postcursor);
 793         tegra_sor_writel(sor, LVDS, 0);
 794
 795         tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
 796         tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
 797
 798         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 799                               DP_PADCTL_TX_PU_ENABLE |
 800                               DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
 801                               DP_PADCTL_TX_PU_ENABLE |
 802                               2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
 803
 804         /* Precharge */
 805         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
 806         udelay(20);
 807
 808         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
 809 }
 810
 811 void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
 812                         const struct tegra_dp_link_config *link_cfg)
 813 {
 814         u32 pad_ctrl = 0;
 815         u32 drive_current = 0;
 816         u32 pre_emphasis = 0;
 817         int err = 0;
 818
 819         switch (link_cfg->lane_count) {
 820         case 4:
 821                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 822                         DP_PADCTL_PD_TXD_1_NO |
 823                         DP_PADCTL_PD_TXD_2_NO |
 824                         DP_PADCTL_PD_TXD_3_NO;
 825                 break;
 826         case 2:
 827                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 828                         DP_PADCTL_PD_TXD_1_NO |
 829                         DP_PADCTL_PD_TXD_2_YES |
 830                         DP_PADCTL_PD_TXD_3_YES;
 831                 break;
 832         case 1:
 833                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 834                         DP_PADCTL_PD_TXD_1_YES |
 835                         DP_PADCTL_PD_TXD_2_YES |
 836                         DP_PADCTL_PD_TXD_3_YES;
 837                 break;
 838         default:
 839                 printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
 840                 return;
 841         }
 842
 843         pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
 844         tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);
 845
 846         err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
 847         if (err) {
 848                 debug("Wait for lane power down failed: %d\n", err);
 849                 return;
 850         }
 851
 852         /* Set to a known-good pre-calibrated setting */
 853         switch (link_cfg->link_bw) {
 854         case SOR_LINK_SPEED_G1_62:
 855         case SOR_LINK_SPEED_G2_7:
 856                 drive_current = 0x13131313;
 857                 pre_emphasis = 0;
 858                 break;
 859         case SOR_LINK_SPEED_G5_4:
 860                 drive_current = 0x19191919;
 861                 pre_emphasis = 0x09090909;
 862         default:
 863                 printf("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);
 864                 return;
 865         }
 866
 867         tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
 868                          drive_current);
 869         tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);
 870 }
 871
 872 int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp)
 873 {
 874         const void *blob = gd->fdt_blob;
 875         struct tegra_dc_sor_data *sor;
 876         int node;
 877
 878         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
 879         if (node < 0)
 880                 return -ENOENT;
 881         sor = calloc(1, sizeof(*sor));
 882         if (!sor)
 883                 return -ENOMEM;
 884         sor->base = (void *)fdtdec_get_addr(blob, node, "reg");
 885
 886         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
 887         if (node < 0)
 888                 return -ENOENT;
 889         sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
 890
 891         sor->power_is_up = 0;
 892         sor->portnum = 0;
 893         *sorp = sor;
 894
 895         return 0;
 896 }