2 * Copyright (c) 2011-2013, NVIDIA Corporation.
4 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/arch/clock.h>
13 #include <asm/arch-tegra/dc.h>
14 #include "displayport.h"
17 DECLARE_GLOBAL_DATA_PTR;
21 #define APBDEV_PMC_DPD_SAMPLE 0x20
22 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE 0
23 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE 1
24 #define APBDEV_PMC_SEL_DPD_TIM 0x1c8
25 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT 0x7f
26 #define APBDEV_PMC_IO_DPD2_REQ 0x1c0
27 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT 25
28 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25)
29 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25)
30 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT 30
31 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30)
32 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30)
33 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30)
34 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30)
35 #define APBDEV_PMC_IO_DPD2_STATUS 0x1c4
36 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT 25
37 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
38 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
40 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
42 return readl((u32 *)sor->base + reg);
45 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
48 writel(val, (u32 *)sor->base + reg);
51 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
52 u32 reg, u32 mask, u32 val)
54 u32 reg_val = tegra_sor_readl(sor, reg);
57 tegra_sor_writel(sor, reg, reg_val);
60 static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
61 u32 mask, u32 exp_val,
62 int poll_interval_us, int timeout_ms)
69 reg_val = tegra_sor_readl(sor, reg);
70 if (((reg_val & mask) == exp_val))
72 udelay(poll_interval_us);
73 } while (get_timer(start) < timeout_ms);
75 debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
76 reg, reg_val, mask, exp_val);
81 int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
86 orig_val = tegra_sor_readl(sor, PWR);
88 reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
89 PWR_NORMAL_STATE_PD; /* normal state only */
91 if (reg_val == orig_val)
92 return 0; /* No update needed */
94 reg_val |= PWR_SETTING_NEW_TRIGGER;
95 tegra_sor_writel(sor, PWR, reg_val);
97 /* Poll to confirm it is done */
98 if (tegra_dc_sor_poll_register(sor, PWR,
99 PWR_SETTING_NEW_DEFAULT_MASK,
100 PWR_SETTING_NEW_DONE,
101 100, TEGRA_SOR_TIMEOUT_MS)) {
102 debug("dc timeout waiting for SOR_PWR = NEW_DONE\n");
109 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
111 const struct tegra_dp_link_config *link_cfg)
115 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
118 reg_val |= DP_LINKCTL_ENABLE_YES;
120 reg_val &= DP_LINKCTL_ENABLE_NO;
122 reg_val &= ~DP_LINKCTL_TUSIZE_MASK;
123 reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);
125 if (link_cfg->enhanced_framing)
126 reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;
128 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
130 switch (training_pattern) {
131 case training_pattern_1:
132 tegra_sor_writel(sor, DP_TPG, 0x41414141);
134 case training_pattern_2:
135 case training_pattern_3:
136 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
137 0x43434343 : 0x42424242;
138 tegra_sor_writel(sor, DP_TPG, reg_val);
141 tegra_sor_writel(sor, DP_TPG, 0x50505050);
146 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
151 /* SOR lane sequencer */
153 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
154 LANE_SEQ_CTL_SEQUENCE_DOWN |
155 LANE_SEQ_CTL_NEW_POWER_STATE_PU;
157 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
158 LANE_SEQ_CTL_SEQUENCE_UP |
159 LANE_SEQ_CTL_NEW_POWER_STATE_PD;
163 reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;
165 reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;
167 tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);
169 if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL,
170 LANE_SEQ_CTL_SETTING_MASK,
171 LANE_SEQ_CTL_SETTING_NEW_DONE,
172 100, TEGRA_SOR_TIMEOUT_MS)) {
173 debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n");
180 static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
181 u32 lane_count, int pu)
185 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
188 switch (lane_count) {
190 reg_val |= (DP_PADCTL_PD_TXD_3_NO |
191 DP_PADCTL_PD_TXD_2_NO);
194 reg_val |= DP_PADCTL_PD_TXD_1_NO;
196 reg_val |= DP_PADCTL_PD_TXD_0_NO;
199 debug("dp: invalid lane number %d\n", lane_count);
203 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
204 tegra_dc_sor_set_lane_count(sor, lane_count);
207 return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
210 void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
215 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
218 reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;
220 reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;
222 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
225 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
228 tegra_sor_writel(sor, PWM_DIV, pwm_div);
229 tegra_sor_writel(sor, PWM_CTL,
230 (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) |
231 PWM_CTL_SETTING_NEW_TRIGGER);
233 if (tegra_dc_sor_poll_register(sor, PWM_CTL,
234 PWM_CTL_SETTING_NEW_SHIFT,
235 PWM_CTL_SETTING_NEW_DONE,
236 100, TEGRA_SOR_TIMEOUT_MS)) {
237 debug("dp: timeout while waiting for SOR PWM setting\n");
241 static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
242 const struct tegra_dp_link_config *link_cfg)
246 tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
248 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
249 reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
250 reg_val &= ~DP_CONFIG_WATERMARK_MASK;
251 reg_val |= link_cfg->watermark;
252 reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;
253 reg_val |= (link_cfg->active_count <<
254 DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
255 reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;
256 reg_val |= (link_cfg->active_frac <<
257 DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
258 if (link_cfg->activepolarity)
259 reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
261 reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
262 reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
263 DP_CONFIG_RD_RESET_VAL_NEGATIVE);
265 tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);
267 /* program h/vblank sym */
268 tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS,
269 DP_AUDIO_HBLANK_SYMBOLS_MASK,
270 link_cfg->hblank_sym);
272 tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS,
273 DP_AUDIO_VBLANK_SYMBOLS_MASK,
274 link_cfg->vblank_sym);
277 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
279 tegra_sor_writel(sor, SUPER_STATE0, 0);
280 tegra_sor_writel(sor, SUPER_STATE0, 1);
281 tegra_sor_writel(sor, SUPER_STATE0, 0);
284 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
286 tegra_sor_writel(sor, STATE0, 0);
287 tegra_sor_writel(sor, STATE0, 1);
288 tegra_sor_writel(sor, STATE0, 0);
291 static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
294 void *pmc_base = sor->pmc_base;
297 writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
298 pmc_base + APBDEV_PMC_DPD_SAMPLE);
299 writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
302 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
303 reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
304 APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
306 reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
307 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
308 APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
309 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
311 writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
314 u32 temp = 10 * 1000;
317 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
322 } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
324 if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {
325 debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
330 writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
331 pmc_base + APBDEV_PMC_DPD_SAMPLE);
337 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
341 reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
343 reg_val |= DP_SPARE_PANEL_INTERNAL;
345 reg_val &= ~DP_SPARE_PANEL_INTERNAL;
347 reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
348 DP_SPARE_SEQ_ENABLE_YES;
349 tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
352 void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
357 reg_val = tegra_sor_readl(sor, CLK_CNTRL);
358 *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)
359 >> CLK_CNTRL_DP_LINK_SPEED_SHIFT;
360 reg_val = tegra_sor_readl(sor,
361 DP_LINKCTL(sor->portnum));
363 switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {
364 case DP_LINKCTL_LANECOUNT_ZERO:
367 case DP_LINKCTL_LANECOUNT_ONE:
370 case DP_LINKCTL_LANECOUNT_TWO:
373 case DP_LINKCTL_LANECOUNT_FOUR:
377 printf("Unknown lane count\n");
381 void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
383 tegra_sor_write_field(sor, CLK_CNTRL,
384 CLK_CNTRL_DP_LINK_SPEED_MASK,
385 link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
388 void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
392 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
393 reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;
394 switch (lane_count) {
398 reg_val |= DP_LINKCTL_LANECOUNT_ONE;
401 reg_val |= DP_LINKCTL_LANECOUNT_TWO;
404 reg_val |= DP_LINKCTL_LANECOUNT_FOUR;
407 /* 0 should be handled earlier. */
408 printf("dp: Invalid lane count %d\n", lane_count);
411 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
415 * The SOR power sequencer does not work for t124 so SW has to
416 * go through the power sequence manually
417 * Power up steps from spec:
418 * STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL
425 static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds)
429 if (sor->power_is_up)
433 tegra_dc_sor_set_link_bandwidth(sor, is_lvds ?
434 CLK_CNTRL_DP_LINK_SPEED_LVDS :
435 CLK_CNTRL_DP_LINK_SPEED_G1_62);
438 tegra_sor_write_field(sor, PLL2,
439 PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
440 PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
441 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
442 PLL2_AUX7_PORT_POWERDOWN_ENABLE |
443 PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
444 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
445 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
446 PLL0_VCOPD_MASK, /* PLLVCOPD */
447 PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
448 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
449 DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
450 DP_PADCTL_PAD_CAL_PD_POWERDOWN);
453 ret = tegra_dc_sor_io_set_dpd(sor, 1);
459 tegra_sor_write_field(sor, PLL2,
460 PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
461 PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
465 tegra_sor_write_field(sor, PLL0,
466 PLL0_PWR_MASK | /* PDPLL */
467 PLL0_VCOPD_MASK, /* PLLVCOPD */
468 PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
470 tegra_sor_write_field(sor, PLL2,
471 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
472 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
476 tegra_sor_write_field(sor, PLL2,
477 PLL2_AUX7_PORT_POWERDOWN_MASK,
478 PLL2_AUX7_PORT_POWERDOWN_DISABLE);
480 sor->power_is_up = 1;
486 static void dump_sor_reg(struct tegra_dc_sor_data *sor)
488 #define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \
489 #a, a, tegra_sor_readl(sor, a));
491 DUMP_REG(SUPER_STATE0);
492 DUMP_REG(SUPER_STATE1);
495 DUMP_REG(NV_HEAD_STATE0(0));
496 DUMP_REG(NV_HEAD_STATE0(1));
497 DUMP_REG(NV_HEAD_STATE1(0));
498 DUMP_REG(NV_HEAD_STATE1(1));
499 DUMP_REG(NV_HEAD_STATE2(0));
500 DUMP_REG(NV_HEAD_STATE2(1));
501 DUMP_REG(NV_HEAD_STATE3(0));
502 DUMP_REG(NV_HEAD_STATE3(1));
503 DUMP_REG(NV_HEAD_STATE4(0));
504 DUMP_REG(NV_HEAD_STATE4(1));
505 DUMP_REG(NV_HEAD_STATE5(0));
506 DUMP_REG(NV_HEAD_STATE5(1));
521 DUMP_REG(LANE_SEQ_CTL);
522 DUMP_REG(SEQ_INST(0));
523 DUMP_REG(SEQ_INST(1));
524 DUMP_REG(SEQ_INST(2));
525 DUMP_REG(SEQ_INST(3));
526 DUMP_REG(SEQ_INST(4));
527 DUMP_REG(SEQ_INST(5));
528 DUMP_REG(SEQ_INST(6));
529 DUMP_REG(SEQ_INST(7));
530 DUMP_REG(SEQ_INST(8));
535 DUMP_REG(DP_LINKCTL(0));
536 DUMP_REG(DP_LINKCTL(1));
539 DUMP_REG(LANE_DRIVE_CURRENT(0));
541 DUMP_REG(LANE4_PREEMPHASIS(0));
542 DUMP_REG(POSTCURSOR(0));
543 DUMP_REG(DP_CONFIG(0));
544 DUMP_REG(DP_CONFIG(1));
547 DUMP_REG(DP_PADCTL(0));
548 DUMP_REG(DP_PADCTL(1));
549 DUMP_REG(DP_DEBUG(0));
550 DUMP_REG(DP_DEBUG(1));
551 DUMP_REG(DP_SPARE(0));
552 DUMP_REG(DP_SPARE(1));
559 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
561 const struct tegra_dp_link_config *link_cfg,
562 const struct display_timing *timing)
564 const int head_num = 0;
565 u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num;
567 u32 vsync_end, hsync_end;
568 u32 vblank_end, hblank_end;
569 u32 vblank_start, hblank_start;
571 reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
572 STATE1_ASY_PROTOCOL_DP_A;
573 reg_val |= STATE1_ASY_SUBOWNER_NONE |
574 STATE1_ASY_CRCMODE_COMPLETE_RASTER;
576 reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
577 reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
578 reg_val |= (link_cfg->bits_per_pixel > 18) ?
579 STATE1_ASY_PIXELDEPTH_BPP_24_444 :
580 STATE1_ASY_PIXELDEPTH_BPP_18_444;
582 tegra_sor_writel(sor, STATE1, reg_val);
585 * Skipping programming NV_HEAD_STATE0, assuming:
586 * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
588 vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
589 timing->vactive.typ + timing->vfront_porch.typ;
590 htotal = timing->hsync_len.typ + timing->hback_porch.typ +
591 timing->hactive.typ + timing->hfront_porch.typ;
593 tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
594 vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
595 htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
597 vsync_end = timing->vsync_len.typ - 1;
598 hsync_end = timing->hsync_len.typ - 1;
599 tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
600 vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
601 hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
603 vblank_end = vsync_end + timing->vback_porch.typ;
604 hblank_end = hsync_end + timing->hback_porch.typ;
605 tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
606 vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
607 hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
609 vblank_start = vblank_end + timing->vactive.typ;
610 hblank_start = hblank_end + timing->hactive.typ;
611 tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
612 vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
613 hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
615 /* TODO: adding interlace mode support */
616 tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
618 tegra_sor_write_field(sor, CSTM,
619 CSTM_ROTCLK_DEFAULT_MASK |
621 2 << CSTM_ROTCLK_SHIFT |
622 is_lvds ? CSTM_LVDS_EN_ENABLE :
623 CSTM_LVDS_EN_DISABLE);
625 tegra_dc_sor_config_pwm(sor, 1024, 1024);
628 static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
630 u32 reg_val = readl(&disp_ctrl->cmd.state_access);
632 writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
633 writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
635 /* Enable DC now - otherwise pure text console may not show. */
636 writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
637 &disp_ctrl->cmd.disp_cmd);
638 writel(reg_val, &disp_ctrl->cmd.state_access);
641 int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
642 const struct tegra_dp_link_config *link_cfg)
646 tegra_sor_write_field(sor, CLK_CNTRL,
647 CLK_CNTRL_DP_CLK_SEL_MASK,
648 CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
650 tegra_sor_write_field(sor, PLL2,
651 PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
652 PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
655 tegra_sor_write_field(sor, PLL3,
656 PLL3_PLLVDD_MODE_MASK,
657 PLL3_PLLVDD_MODE_V3_3);
658 tegra_sor_writel(sor, PLL0,
659 0xf << PLL0_ICHPMP_SHFIT |
660 0x3 << PLL0_VCOCAP_SHIFT |
661 PLL0_PLLREG_LEVEL_V45 |
662 PLL0_RESISTORSEL_EXT |
663 PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
664 tegra_sor_write_field(sor, PLL2,
666 PLL2_AUX9_LVDSEN_OVERRIDE |
667 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
668 PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
669 PLL2_AUX9_LVDSEN_OVERRIDE |
670 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
671 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
672 PLL1_TMDS_TERM_ENABLE);
674 if (tegra_dc_sor_poll_register(sor, PLL2,
675 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
676 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
677 100, TEGRA_SOR_TIMEOUT_MS)) {
678 printf("DP failed to lock PLL\n");
682 tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
683 PLL2_AUX7_PORT_POWERDOWN_MASK,
684 PLL2_AUX2_OVERRIDE_POWERDOWN |
685 PLL2_AUX7_PORT_POWERDOWN_DISABLE);
687 ret = tegra_dc_sor_power_up(sor, 0);
689 debug("DP failed to power up\n");
693 /* re-enable SOR clock */
694 clock_sor_enable_edp_clock();
697 tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
699 tegra_dc_sor_set_dp_mode(sor, link_cfg);
700 debug("%s ret\n", __func__);
705 int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
706 const struct tegra_dp_link_config *link_cfg,
707 const struct display_timing *timing)
709 const void *blob = gd->fdt_blob;
710 struct dc_ctlr *disp_ctrl;
714 /* Use the first display controller */
715 debug("%s\n", __func__);
716 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
719 disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
721 tegra_dc_sor_enable_dc(disp_ctrl);
722 tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
724 writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
725 writel(0x9f, &disp_ctrl->cmd.state_ctrl);
727 writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
728 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
729 &disp_ctrl->cmd.disp_pow_ctrl);
731 reg_val = tegra_sor_readl(sor, TEST);
732 if (reg_val & TEST_ATTACHED_TRUE)
735 tegra_sor_writel(sor, SUPER_STATE1,
736 SUPER_STATE1_ATTACHED_NO);
739 * Enable display2sor clock at least 2 cycles before DC start,
740 * to clear sor internal valid signal.
742 writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
743 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
744 writel(0, &disp_ctrl->disp.disp_win_opt);
745 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
748 tegra_dc_sor_update(sor);
749 tegra_sor_writel(sor, SUPER_STATE1,
750 SUPER_STATE1_ATTACHED_YES);
751 tegra_sor_writel(sor, SUPER_STATE1,
752 SUPER_STATE1_ATTACHED_YES |
753 SUPER_STATE1_ASY_HEAD_OP_AWAKE |
754 SUPER_STATE1_ASY_ORMODE_NORMAL);
755 tegra_dc_sor_super_update(sor);
758 reg_val = readl(&disp_ctrl->cmd.state_access);
759 writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
760 writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
761 &disp_ctrl->cmd.disp_cmd);
762 writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
763 writel(reg_val, &disp_ctrl->cmd.state_access);
765 if (tegra_dc_sor_poll_register(sor, TEST,
766 TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
767 TEST_ACT_HEAD_OPMODE_AWAKE,
769 TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
770 printf("dc timeout waiting for OPMOD = AWAKE\n");
773 debug("%s: sor is attached\n", __func__);
779 debug("%s: ret=%d\n", __func__, 0);
784 void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
785 const struct tegra_dp_link_config *link_cfg)
787 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
788 link_cfg->drive_current);
789 tegra_sor_writel(sor, PR(sor->portnum),
790 link_cfg->preemphasis);
791 tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
792 link_cfg->postcursor);
793 tegra_sor_writel(sor, LVDS, 0);
795 tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
796 tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
798 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
799 DP_PADCTL_TX_PU_ENABLE |
800 DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
801 DP_PADCTL_TX_PU_ENABLE |
802 2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
805 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
808 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
811 void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
812 const struct tegra_dp_link_config *link_cfg)
815 u32 drive_current = 0;
816 u32 pre_emphasis = 0;
819 switch (link_cfg->lane_count) {
821 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
822 DP_PADCTL_PD_TXD_1_NO |
823 DP_PADCTL_PD_TXD_2_NO |
824 DP_PADCTL_PD_TXD_3_NO;
827 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
828 DP_PADCTL_PD_TXD_1_NO |
829 DP_PADCTL_PD_TXD_2_YES |
830 DP_PADCTL_PD_TXD_3_YES;
833 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
834 DP_PADCTL_PD_TXD_1_YES |
835 DP_PADCTL_PD_TXD_2_YES |
836 DP_PADCTL_PD_TXD_3_YES;
839 printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
843 pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
844 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);
846 err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
848 debug("Wait for lane power down failed: %d\n", err);
852 /* Set to a known-good pre-calibrated setting */
853 switch (link_cfg->link_bw) {
854 case SOR_LINK_SPEED_G1_62:
855 case SOR_LINK_SPEED_G2_7:
856 drive_current = 0x13131313;
859 case SOR_LINK_SPEED_G5_4:
860 drive_current = 0x19191919;
861 pre_emphasis = 0x09090909;
863 printf("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);
867 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
869 tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);
872 int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp)
874 const void *blob = gd->fdt_blob;
875 struct tegra_dc_sor_data *sor;
878 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
881 sor = calloc(1, sizeof(*sor));
884 sor->base = (void *)fdtdec_get_addr(blob, node, "reg");
886 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
889 sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
891 sor->power_is_up = 0;