git.sur5r.net Git - u-boot/blob - drivers/w83c553f.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
  26  * write protection (for flash) in function 0 of the chip.
  27  * Enabling function 1 (IDE controller of the chip.
  28  */
  29
  30 #include <common.h>
  31 #include <config.h>
  32
  33 #ifdef CFG_WINBOND_83C553
  34
  35 #include <asm/io.h>
  36 #include <pci.h>
  37
  38 #include <w83c553f.h>
  39
  40 #define out8(addr,val)  do { \
  41                         out_8((u8*) (addr),(val)); udelay(1); \
  42                         } while (0)
  43 #define out16(addr,val) do { \
  44                         out_be16((u16*) (addr),(val)); udelay(1); \
  45                         } while (0)
  46
  47 extern uint ide_bus_offset[CFG_IDE_MAXBUS];
  48
  49 void initialise_pic(void);
  50 void initialise_dma(void);
  51
  52 void initialise_w83c553f(void)
  53 {
  54         pci_dev_t devbusfn;
  55         unsigned char reg8;
  56         unsigned short reg16;
  57         unsigned int reg32;
  58
  59         devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
  60         if (devbusfn == -1)
  61         {
  62                 printf("Error: Cannot find W83C553F controller on any PCI bus.");
  63                 return;
  64         }
  65
  66         pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
  67         reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  68         pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
  69
  70         pci_read_config_byte(devbusfn, WINBOND_IPADCR, &reg8);
  71         /* 16 MB ISA memory space */
  72         reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
  73         reg8 &= ~IPADCR_MBE512;
  74         pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
  75
  76         pci_read_config_byte(devbusfn, WINBOND_CSCR, &reg8);
  77         /* switch off BIOS write protection */
  78         reg8 |= CSCR_UBIOSCSE;
  79         reg8 &= ~CSCR_BIOSWP;
  80         pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
  81
  82         /*
  83          * Interrupt routing:
  84          *  - IDE  -> IRQ 9/0
  85          *  - INTA -> IRQ 10
  86          *  - INTB -> IRQ 11
  87          *  - INTC -> IRQ 14
  88          *  - INTD -> IRQ 15
  89          */
  90         pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
  91         pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
  92
  93         /*
  94          * Read IDE bus offsets from function 1 device.
  95          * We must unmask the LSB indicating that ist is an IO address.
  96          */
  97         devbusfn |= PCI_BDF(0,0,1);
  98
  99         /*
 100          * Switch off legacy IRQ for IDE and IDE port 1.
 101          */
 102         pci_write_config_byte(devbusfn, 0x09, 0x8F);
 103
 104         pci_read_config_dword(devbusfn, WINDOND_IDECSR, &reg32);
 105         reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
 106         pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
 107
 108         pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
 109         ide_bus_offset[0] &= ~1;
 110 #if CFG_IDE_MAXBUS > 1
 111         pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
 112         ide_bus_offset[1] &= ~1;
 113 #endif
 114
 115         /*
 116          * Enable function 1, IDE -> busmastering and IO space access
 117          */
 118         pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
 119         reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
 120         pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
 121
 122         /*
 123          * Initialise ISA interrupt controller
 124          */
 125         initialise_pic();
 126
 127         /*
 128          * Initialise DMA controller
 129          */
 130         initialise_dma();
 131 }
 132
 133 void initialise_pic(void)
 134 {
 135         out8(W83C553F_PIC1_ICW1, 0x11);
 136         out8(W83C553F_PIC1_ICW2, 0x08);
 137         out8(W83C553F_PIC1_ICW3, 0x04);
 138         out8(W83C553F_PIC1_ICW4, 0x01);
 139         out8(W83C553F_PIC1_OCW1, 0xfb);
 140         out8(W83C553F_PIC1_ELC, 0x20);
 141
 142         out8(W83C553F_PIC2_ICW1, 0x11);
 143         out8(W83C553F_PIC2_ICW2, 0x08);
 144         out8(W83C553F_PIC2_ICW3, 0x02);
 145         out8(W83C553F_PIC2_ICW4, 0x01);
 146         out8(W83C553F_PIC2_OCW1, 0xff);
 147         out8(W83C553F_PIC2_ELC, 0xce);
 148
 149         out8(W83C553F_TMR1_CMOD, 0x74);
 150
 151         out8(W83C553F_PIC2_OCW1, 0x20);
 152         out8(W83C553F_PIC1_OCW1, 0x20);
 153
 154         out8(W83C553F_PIC2_OCW1, 0x2b);
 155         out8(W83C553F_PIC1_OCW1, 0x2b);
 156 }
 157
 158 void initialise_dma(void)
 159 {
 160         unsigned int channel;
 161         unsigned int rvalue1, rvalue2;
 162
 163         /* perform a H/W reset of the devices */
 164
 165         out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
 166         out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
 167
 168         /* initialise all channels to a sane state */
 169
 170         for (channel = 0; channel < 4; channel++) {
 171                 /*
 172                  * dependent upon the channel, setup the specifics:
 173                  *
 174                  * demand
 175                  * address-increment
 176                  * autoinitialize-disable
 177                  * verify-transfer
 178                  */
 179
 180                 switch (channel) {
 181                 case 0:
 182                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
 183                         rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
 184                         break;
 185                 case 1:
 186                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 187                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 188                         break;
 189                 case 2:
 190                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 191                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 192                         break;
 193                 case 3:
 194                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 195                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 196                         break;
 197                 default:
 198                         rvalue1 = 0x00;
 199                         rvalue2 = 0x00;
 200                         break;
 201                 }
 202
 203                 /* write to write mode registers */
 204
 205                 out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
 206                 out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
 207         }
 208
 209         /* enable all channels */
 210
 211         out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
 212         out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
 213         /*
 214          * initialize the global DMA configuration
 215          *
 216          * DACK# active low
 217          * DREQ active high
 218          * fixed priority
 219          * channel group enable
 220          */
 221
 222         out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
 223         out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
 224 }
 225
 226 #endif /* CFG_WINBOND_83C553 */