5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * SPDX-License-Identifier: GPL-2.0
11 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
13 * commit 2d991a164a61858012651e13c59521975504e260
14 * Author: Bill Pemberton <wfp5p@virginia.edu>
15 * Date: Mon Nov 19 13:21:41 2012 -0500
17 * watchdog: remove use of __devinit
19 * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
22 * Author: MontaVista Software, Inc.
23 * <gdavis@mvista.com> or <source@mvista.com>
27 * 20030527: George G. Davis <gdavis@mvista.com>
28 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
29 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
30 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
32 * Copyright (c) 2004 Texas Instruments.
33 * 1. Modified to support OMAP1610 32-KHz watchdog timer
34 * 2. Ported to 2.6 kernel
36 * Copyright (c) 2005 David Brownell
37 * Use the driver model and standard identifiers; handle bigger timeouts.
42 #include <asm/arch/hardware.h>
44 #include <asm/processor.h>
45 #include <asm/arch/cpu.h>
47 /* Hardware timeout in seconds */
48 #define WDT_HW_TIMEOUT 60
50 static unsigned int wdt_trgr_pattern = 0x1234;
52 void hw_watchdog_reset(void)
54 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
57 * Somebody just triggered watchdog reset and write to WTGR register
58 * is in progress. It is resetting right now, no need to trigger it
61 if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
64 wdt_trgr_pattern = ~wdt_trgr_pattern;
65 writel(wdt_trgr_pattern, &wdt->wdtwtgr);
68 * Don't wait for posted write to complete, i.e. don't check
69 * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
70 * WTGR register outside of this func, and if entering it
71 * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
72 * was just triggered. This prevents us from wasting time in busy
73 * polling of WDT_WWPS_PEND_WTGR bit.
77 static int omap_wdt_set_timeout(unsigned int timeout)
79 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
80 u32 pre_margin = GET_WLDR_VAL(timeout);
82 /* just count up at 32 KHz */
83 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
86 writel(pre_margin, &wdt->wdtwldr);
87 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
93 void hw_watchdog_disable(void)
95 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
100 writel(0xAAAA, &wdt->wdtwspr);
101 while (readl(&wdt->wdtwwps) != 0x0)
103 writel(0x5555, &wdt->wdtwspr);
104 while (readl(&wdt->wdtwwps) != 0x0)
108 void hw_watchdog_init(void)
110 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
113 * Make sure the watchdog is disabled. This is unfortunately required
114 * because writing to various registers with the watchdog running has no
117 hw_watchdog_disable();
119 /* initialize prescaler */
120 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
123 writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
124 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
127 omap_wdt_set_timeout(WDT_HW_TIMEOUT);
129 /* Sequence to enable the watchdog */
130 writel(0xBBBB, &wdt->wdtwspr);
131 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
134 writel(0x4444, &wdt->wdtwspr);
135 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)