2 * TNETV107X: Watchdog timer implementation (for reset)
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
11 #define MAX_DIV 0xFFFE0001
15 #define KICK_LOCK_1 0x5555
16 #define KICK_LOCK_2 0xaaaa
20 #define CHANGE_LOCK_1 0x6666
21 #define CHANGE_LOCK_2 0xbbbb
25 #define DISABLE_LOCK_1 0x7777
26 #define DISABLE_LOCK_2 0xcccc
27 #define DISABLE_LOCK_3 0xdddd
31 #define PRESCALE_LOCK_1 0x5a5a
32 #define PRESCALE_LOCK_2 0xa5a5
36 static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
38 #define wdt_reg_read(reg) __raw_readl(®s->reg)
39 #define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg)
41 static int write_prescale_reg(unsigned long prescale_value)
43 wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
44 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
47 wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
48 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
51 wdt_reg_write(prescale, prescale_value);
56 static int write_change_reg(unsigned long initial_timer_value)
58 wdt_reg_write(change_lock, CHANGE_LOCK_1);
59 if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
62 wdt_reg_write(change_lock, CHANGE_LOCK_2);
63 if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
66 wdt_reg_write(change, initial_timer_value);
71 static int wdt_control(unsigned long disable_value)
73 wdt_reg_write(disable_lock, DISABLE_LOCK_1);
74 if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
77 wdt_reg_write(disable_lock, DISABLE_LOCK_2);
78 if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
81 wdt_reg_write(disable_lock, DISABLE_LOCK_3);
82 if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
85 wdt_reg_write(disable, disable_value);
89 static int wdt_set_period(unsigned long msec)
91 unsigned long change_value, count_value;
92 unsigned long prescale_value = 1;
93 unsigned long refclk_khz, maxdiv;
96 refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
97 maxdiv = (MAX_DIV / refclk_khz);
99 if ((!msec) || (msec > maxdiv))
102 count_value = refclk_khz * msec;
103 if (count_value > 0xffff) {
104 change_value = count_value / 0xffff + 1;
105 prescale_value = count_value / change_value;
107 change_value = count_value;
110 ret = write_prescale_reg(prescale_value - 1);
114 ret = write_change_reg(change_value);
121 unsigned long last_wdt = -1;
123 int wdt_start(unsigned long msecs)
126 ret = wdt_control(0);
129 ret = wdt_set_period(msecs);
132 ret = wdt_control(1);
143 return wdt_control(0);
148 wdt_reg_write(kick_lock, KICK_LOCK_1);
149 if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
152 wdt_reg_write(kick_lock, KICK_LOCK_2);
153 if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
156 wdt_reg_write(kick, 1);
160 void reset_cpu(ulong addr)
162 clk_enable(TNETV107X_LPSC_WDT_ARM);