1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011-2013 Xilinx Inc.
8 #include <asm/microblaze_intc.h>
9 #include <asm/processor.h>
12 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
13 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
14 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
15 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
17 struct watchdog_regs {
23 static struct watchdog_regs *watchdog_base =
24 (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
26 void hw_watchdog_reset(void)
30 /* Read the current contents of TCSR0 */
31 reg = readl(&watchdog_base->twcsr0);
33 /* Clear the watchdog WDS bit */
34 if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
35 writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
38 void hw_watchdog_disable(void)
42 /* Read the current contents of TCSR0 */
43 reg = readl(&watchdog_base->twcsr0);
45 writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
46 writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
48 puts("Watchdog disabled!\n");
51 static void hw_watchdog_isr(void *arg)
56 void hw_watchdog_init(void)
60 writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
61 &watchdog_base->twcsr0);
62 writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
64 ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
65 hw_watchdog_isr, NULL);
67 puts("Watchdog IRQ registration failed.");