3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <ppc_asm.tmpl>
28 #include <asm/cache.h>
30 #include "test_burst.h"
34 * void mmu_init(void);
36 * This function turns the MMU on
38 * Three 8 MByte regions are mapped 1:1, uncached
39 * - SDRAM lower 8 MByte
40 * - SDRAM higher 8 MByte
45 tlbia /* Invalidate all TLB entries */
47 mtspr MI_CTR, r8 /* Set instruction control to zero */
49 mtspr MD_CTR, r8 /* Set data TLB control */
51 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
52 * we can load the instruction and data TLB registers with the
55 li r8, MI_EVALID /* Create EPN for address 0 */
58 li r8, MI_PS8MEG /* Set 8M byte page */
59 ori r8, r8, MI_SVALID /* Make it valid */
62 li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */
63 mtspr MI_RPN, r8 /* Store TLB entry */
65 lis r8, MI_Kp@h /* Set the protection mode */
69 /* Now map the higher 8 Meg into the TLBs. For this quick hack,
70 * we can load the instruction and data TLB registers with the
73 lwz r9,20(r2) /* gd->ram_size */
76 mr r8, r9 /* Higher 8 Meg in SDRAM */
77 ori r8, r8, MI_EVALID /* Mark page valid */
80 li r8, MI_PS8MEG /* Set 8M byte page */
81 ori r8, r8, MI_SVALID /* Make it valid */
85 ori r8, r8, MI_BOOTINIT|0x2
86 mtspr MI_RPN, r8 /* Store TLB entry */
88 lis r8, MI_Kp@h /* Set the protection mode */
92 /* Map another 8 MByte at the IMMR to get the processor
93 * internal registers (among other things).
95 mfspr r9, 638 /* Get current IMMR */
96 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
98 mr r8, r9 /* Create vaddr for TLB */
99 ori r8, r8, MD_EVALID /* Mark it valid */
101 li r8, MD_PS8MEG /* Set 8M byte page */
102 ori r8, r8, MD_SVALID /* Make it valid */
104 mr r8, r9 /* Create paddr for TLB */
105 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
108 /* We now have the lower and higher 8 Meg mapped into TLB entries,
109 * and the caches ready to work.
112 ori r0,r0,MSR_DR|MSR_IR
117 rfi /* enables MMU */
120 * void caches_init(void);
126 mfspr r3, IC_CST /* Clear error bits */
129 lis r3, IDC_UNALL@h /* Unlock all */
133 lis r3, IDC_INVALL@h /* Invalidate all */
137 lis r3, IDC_ENABLE@h /* Enable all */
144 * void flush_dcache_range(unsigned long start, unsigned long stop);
146 .global flush_dcache_range
148 li r5,CACHE_LINE_SIZE-1
152 srwi. r4,r4,LG_CACHE_LINE_SIZE
157 addi r3,r3,CACHE_LINE_SIZE
159 sync /* wait for dcbf's to get to ram */
163 * void disable_interrupts(void);
165 .global disable_interrupts