1 /* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
2 /*----------------------------------------------------------------------------+
3 | This source code is dual-licensed. You may use it under the terms of the
4 | GNU General Public License version 2, or under the license below.
6 | This source code has been made available to you by IBM on an AS-IS
7 | basis. Anyone receiving this source is licensed under IBM
8 | copyrights to use it in any way he or she deems fit, including
9 | copying it, modifying it, compiling it, and redistributing it either
10 | with or without modifications. No license under IBM patents or
11 | patent applications is to be implied by the copyright license.
13 | Any user of this software should understand that IBM cannot provide
14 | technical support for this software and will not be responsible for
15 | any consequences resulting from the use of this software.
17 | Any person who transfers this source code or any derivative work
18 | must include the IBM copyright notice, this paragraph, and the
19 | preceding two paragraphs in the transferred software.
21 | COPYRIGHT I B M CORPORATION 1999
22 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
23 +----------------------------------------------------------------------------*/
24 /*----------------------------------------------------------------------------+
28 | Function: Header file for the MAL (MADMAL) macro on the 405GP.
34 | Date Description of Change BY
35 | --------- --------------------- ---
36 | 29-Apr-99 Created MKW
38 +----------------------------------------------------------------------------*/
39 /*----------------------------------------------------------------------------+
40 | 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
41 | Added register bit definitions to support multiple channels
42 +----------------------------------------------------------------------------*/
45 /* MADMAL transmit and receive status/control bits */
46 /* for COMMAC bits, refer to the COMMAC header file */
48 #define MAL_TX_CTRL_READY 0x8000
49 #define MAL_TX_CTRL_WRAP 0x4000
50 #define MAL_TX_CTRL_CM 0x2000
51 #define MAL_TX_CTRL_LAST 0x1000
52 #define MAL_TX_CTRL_INTR 0x0400
54 #define MAL_RX_CTRL_EMPTY 0x8000
55 #define MAL_RX_CTRL_WRAP 0x4000
56 #define MAL_RX_CTRL_CM 0x2000
57 #define MAL_RX_CTRL_LAST 0x1000
58 #define MAL_RX_CTRL_FIRST 0x0800
59 #define MAL_RX_CTRL_INTR 0x0400
61 /* Configuration Reg */
62 #define MAL_CR_MMSR 0x80000000
63 #define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
64 #define MAL_CR_PLBP_2 0x00800000
65 #define MAL_CR_PLBP_3 0x00C00000 /* highest */
66 #define MAL_CR_GA 0x00200000
67 #define MAL_CR_OA 0x00100000
68 #define MAL_CR_PLBLE 0x00080000
69 #define MAL_CR_PLBLT_1 0x00040000
70 #define MAL_CR_PLBLT_2 0x00020000
71 #define MAL_CR_PLBLT_3 0x00010000
72 #define MAL_CR_PLBLT_4 0x00008000
73 #define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
74 #define MAL_CR_PLBB 0x00004000
75 #define MAL_CR_OPBBL 0x00000080
76 #define MAL_CR_EOPIE 0x00000004
77 #define MAL_CR_LEA 0x00000002
78 #define MAL_CR_MSD 0x00000001
80 /* Error Status Reg */
81 #define MAL_ESR_EVB 0x80000000
82 #define MAL_ESR_CID 0x40000000
83 #define MAL_ESR_DE 0x00100000
84 #define MAL_ESR_ONE 0x00080000
85 #define MAL_ESR_OTE 0x00040000
86 #define MAL_ESR_OSE 0x00020000
87 #define MAL_ESR_PEIN 0x00010000
88 /* same bit position as the IER */
90 #define MAL_ESR_DEI 0x00000010
91 #define MAL_ESR_ONEI 0x00000008
92 #define MAL_ESR_OTEI 0x00000004
93 #define MAL_ESR_OSEI 0x00000002
94 #define MAL_ESR_PBEI 0x00000001
97 #if defined(CONFIG_440SPE) || \
98 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
99 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
100 defined(CONFIG_405EX)
101 #define MAL_IER_PT 0x00000080
102 #define MAL_IER_PRE 0x00000040
103 #define MAL_IER_PWE 0x00000020
104 #define MAL_IER_DE 0x00000010
105 #define MAL_IER_OTE 0x00000004
106 #define MAL_IER_OE 0x00000002
107 #define MAL_IER_PE 0x00000001
109 #define MAL_IER_DE 0x00000010
110 #define MAL_IER_NE 0x00000008
111 #define MAL_IER_TE 0x00000004
112 #define MAL_IER_OPBE 0x00000002
113 #define MAL_IER_PLBE 0x00000001
116 /* MAL Channel Active Set and Reset Registers */
117 #define MAL_TXRX_CASR (0x80000000)
119 #define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
122 /* MAL Buffer Descriptor structure */
124 short ctrl; /* MAL / Commac status control bits */
125 short data_len; /* Max length is 4K-1 (12 bits) */
126 char *data_ptr; /* pointer to actual data buffer */