1 /*****************************************************************************/
5 /* Internal include file, do not use directly */
7 /* The Peripheral Interface Adapter (PIA) chip (a 6520 or 6820) provides */
8 /* parallel I/O interfacing; it was used in Atari 400/800 and Commodore PET */
9 /* family of computers, for joystick and some interrupts. */
10 /* Sources; various + Wikpedia article on "Peripheral Interface Adapter". */
13 /* (C) 2000 Freddy Offenga <taf_offenga@yahoo.com> */
14 /* 2019-01-17: Bill Kendrick <nbs@sonic.net>: Defines for registers */
17 /* This software is provided 'as-is', without any expressed or implied */
18 /* warranty. In no event will the authors be held liable for any damages */
19 /* arising from the use of this software. */
21 /* Permission is granted to anyone to use this software for any purpose, */
22 /* including commercial applications, and to alter it and redistribute it */
23 /* freely, subject to the following restrictions: */
25 /* 1. The origin of this software must not be misrepresented; you must not */
26 /* claim that you wrote the original software. If you use this software */
27 /* in a product, an acknowledgment in the product documentation would be */
28 /* appreciated but is not required. */
29 /* 2. Altered source versions must be plainly marked as such, and must not */
30 /* be misrepresented as being the original software. */
31 /* 3. This notice may not be removed or altered from any source */
34 /*****************************************************************************/
42 /* Define a structure with the PIA register offsets */
44 unsigned char porta; /* port A data r/w */
45 unsigned char portb; /* port B data r/w */
46 unsigned char pactl; /* port A control */
47 unsigned char pbctl; /* port B control */
51 /*****************************************************************************/
52 /* PORTA and PORTB register bits */
53 /*****************************************************************************/
55 /* See also: "JOY_xxx_MASK" in "atari.h" */
57 /* Paddle 0-3 triggers (per PORTA bits) */
58 #define PORTA_PTRIG3 0x80
59 #define PORTA_PTRIG2 0x40
60 #define PORTA_PTRIG1 0x08
61 #define PORTA_PTRIG0 0x04
64 /* On the Atari 400/800, PORTB is the same as PORTA, but for controller ports 3 & 4. */
66 /* Paddle 4-7 triggers (per PORTB bits); only 400/800 had four controller ports */
67 #define PORTB_PTRIG7 0x80
68 #define PORTB_PTRIG6 0x40
69 #define PORTB_PTRIG5 0x08
70 #define PORTB_PTRIG4 0x04
73 /* On the XL series of computers, PORTB has been changed to a memory and
74 ** LED control (1200XL model only) register (read/write):
77 /* If set, the built-in OS is enabled, and occupies the address range $C000-$FFFF
78 ** (except that the area $D000-$D7FF will only access the hardware registers.)
79 ** If clear, RAM is enabled in this area (again, save for the hole.)
81 #define PORTB_OSROM 0x01
83 /* If set, RAM is enabled for the address range $A000-$BFFF.
84 ** If clear, the built-in BASIC ROM is enabled at this address.
85 ** And if there is a cartridge installed in the computer, it makes no difference.
87 #define PORTB_BASICROM 0x02
89 /* If set, the corresponding LED is turned off. If clear, the LED will be on.
92 #define PORTB_LED1 0x04
93 #define PORTB_LED2 0x08
96 /* On the XE series of computers, PORTB is a bank-selected memory control register (read/write): */
98 /* These bits determine which memory bank is visible to the CPU and/or ANTIC chip
99 ** when their Bank Switch bit is set. There are four possible banks of 16KB each.
101 #define PORTB_BANKSELECT1 0x00
102 #define PORTB_BANKSELECT2 0x04
103 #define PORTB_BANKSELECT3 0x08
104 #define PORTB_BANKSELECT4 0x0C
106 /* If set, the CPU and/or ANTIC chip will access bank-switched memory mapped to the
107 ** address range $4000-$7FFF.
108 ** If clear, the CPU and/or ANTIC will see normal memory in this region.
110 #define PORTB_BANKSWITCH_CPU 0x10
111 #define PORTB_BANKSWITCH_ANTIC 0x20
113 /* If set, RAM is enabled for the address range $5000-$57FF.
114 ** If clear, the self-test ROM (physically located at $D000-$D7FF, under the hardware registers)
115 ** is remapped to this memory area.
117 #define PORTB_SELFTEST 0x80
120 /*****************************************************************************/
121 /* PACTL and PBCTL register bits */
122 /*****************************************************************************/
124 /* (W) Peripheral PA1/PB1 interrupt (IRQ) ("peripheral proceed line available") enable.
125 ** One equals enable. Set by the OS but available to the user; reset on powerup.
126 ** (PxCTL_IRQ_STATUS (R) bit will get set upon interrupt occurance)
128 #define PxCTL_IRQ_ENABLE 0x01 /* bit 0 */
130 /* Note: Bit 1 is always set to */
132 /* (W) Controls PORTA/PORTB addressing
133 ** 1 = PORTA/PORTB register; read/write to controller port
134 ** 0 = direction control register; write to direction controls
135 ** (allows setting data flow; write 0s & 1s to PORTA/PORTB bits
136 ** to set which port's pins are read (input), or write (output),
139 #define PxCTL_ADDRESSING 0x04 /* bit 2 */
141 /* (W) Peripheral motor control line; Turn the cassette on or off
142 ** (PACTL-specific register bit)
146 #define PACTL_MOTOR_CONTROL 0x08 /* bit 3 */
148 /* Peripheral command identification (serial bus command line)
149 ** (PBCTL-specific register bit)
151 #define PBCTL_PERIPH_CMD_IDENT 0x08 /* bit 3 */
153 /* Note: Bits 4 & 5 are always set to 1 */
155 /* Note: Bit 6 is always set to 0 */
157 /* (R) Peripheral interrupt (IRQ) status bit.
158 ** Set by Peripherals (PORTA / PORTB). Reset by reading from PORTA / PORTB.
159 ** PACTL's is interrupt status of PROCEED
160 ** PBCTL's is interrupt status of SIO
162 #define PxCTL_IRQ_STATUS 0x80