1 /*****************************************************************************/
5 /* Internal include file, do not use directly */
7 /* POKEY, Pot Keyboard Integrated Circuit, is a digital I/O chip designed */
8 /* for the Atari 8-bit family of home computers; it combines functions for */
9 /* sampling (ADC) potentiometers (such as game paddles) and scan matrices of */
10 /* switches (such as a computer keyboard) as well as sound generation. */
11 /* It produces four voices of distinctive square wave sound, either as clear */
12 /* tones or modified with a number of distortion settings. - Wikipedia */
13 /* "POKEY" article. */
16 /* (C) 2000 Freddy Offenga <taf_offenga@yahoo.com> */
17 /* 2019-01-16: Bill Kendrick <nbs@sonic.net>: More defines for registers */
20 /* This software is provided 'as-is', without any expressed or implied */
21 /* warranty. In no event will the authors be held liable for any damages */
22 /* arising from the use of this software. */
24 /* Permission is granted to anyone to use this software for any purpose, */
25 /* including commercial applications, and to alter it and redistribute it */
26 /* freely, subject to the following restrictions: */
28 /* 1. The origin of this software must not be misrepresented; you must not */
29 /* claim that you wrote the original software. If you use this software */
30 /* in a product, an acknowledgment in the product documentation would be */
31 /* appreciated but is not required. */
32 /* 2. Altered source versions must be plainly marked as such, and must not */
33 /* be misrepresented as being the original software. */
34 /* 3. This notice may not be removed or altered from any source */
37 /*****************************************************************************/
46 /*****************************************************************************/
47 /* Define a structure with the POKEY register offsets for write (W) */
48 /*****************************************************************************/
50 struct __pokey_write {
51 unsigned char audf1; /* audio channel #1 frequency */
52 unsigned char audc1; /* audio channel #1 control */
53 unsigned char audf2; /* audio channel #2 frequency */
54 unsigned char audc2; /* audio channel #2 control */
55 unsigned char audf3; /* audio channel #3 frequency */
56 unsigned char audc3; /* audio channel #3 control */
57 unsigned char audf4; /* audio channel #4 frequency */
58 unsigned char audc4; /* audio channel #4 control */
59 unsigned char audctl; /* audio control */
60 unsigned char stimer; /* start pokey timers */
63 /* reset serial port status reg.;
64 ** Reset BITs 5 - 7 of the serial port status register (SKCTL) to "1"
67 unsigned char potgo; /* start paddle scan sequence (see "ALLPOT") */
68 unsigned char unuse1; /* unused */
69 unsigned char serout; /* serial port data output */
70 unsigned char irqen; /* interrupt request enable */
71 unsigned char skctl; /* serial port control */
75 /*****************************************************************************/
76 /* (W) AUDC1-4 register values */
77 /*****************************************************************************/
79 /* Meaningful values for the distortion bits.
80 ** The first process is to divide the clock value by the frequency,
81 ** then mask the output using the polys in the order below;
82 ** finally, the result is divided by two.
84 #define AUDC_POLYS_5_17 0x00
85 #define AUDC_POLYS_5 0x20 /* Same as 0x60 */
86 #define AUDC_POLYS_5_4 0x40
87 #define AUDC_POLYS_17 0x80
88 #define AUDC_POLYS_NONE 0xA0 /* Same as 0xE0 */
89 #define AUDC_POLYS_4 0xC0
91 /* When set, the volume value in AUDC1-4 bits 0-3 is sent directly to the speaker;
92 ** it is not modulated with the frequency specified in the AUDF1-4 registers.
93 ** (See "De Re Atari" Chapter 7: Sound)
95 #define AUDC_VOLUME_ONLY 0x10
98 /*****************************************************************************/
99 /* (W) AUDCTL register values */
100 /*****************************************************************************/
102 #define AUDCTL_CLOCKBASE_15HZ 0x01 /* Switch main clock base from 64 KHz to 15 KHz */
103 #define AUDCTL_HIGHPASS_CHAN2 0x02 /* Insert high pass filter into channel two, clocked by channel four */
104 #define AUDCTL_HIGHPASS_CHAN1 0x04 /* Insert high pass filter into channel one, clocked by channel two */
105 #define AUDCTL_JOIN_CHAN34 0x08 /* Join channels four and three (16 bit) */
106 #define AUDCTL_JOIN_CHAN12 0x10 /* Join channels two and one (16 bit) */
107 #define AUDCTL_CLOCK_CHAN3_179MHZ 0x20 /* Clock channel three with 1.79 MHz */
108 #define AUDCTL_CLOCK_CHAN1_179MHZ 0x40 /* Clock channel one with 1.79 MHz */
109 #define AUDCTL_9BIT_POLY 0x80 /* Makes the 17 bit poly counter into nine bit poly (see also: RANDOM) */
112 /*****************************************************************************/
113 /* (W) IRQEN register values */
114 /*****************************************************************************/
116 #define IRQEN_TIMER_1 0x01 /* The POKEY timer one interrupt is enabled */
117 #define IRQEN_TIMER_2 0x02 /* The POKEY timer two interrupt is enabled */
118 #define IRQEN_TIMER_4 0x04 /* The POKEY timer four interrupt is enabled */
119 #define IRQEN_SERIAL_TRANS_FINISHED 0x08 /* The serial out transmission finished interrupt is enabled */
120 #define IRQEN_SERIAL_OUT_DATA_REQUIRED 0x10 /* The serial output data required interrupt is enabled */
121 #define IRQEN_SERIAL_IN_DATA_READY 0x20 /* The serial input data ready interrupt is enabled. */
122 #define IRQEN_OTHER_KEY 0x40 /* The "other key" interrupt is enabled */
123 #define IRQEN_BREAK_KEY 0x80 /* The BREAK key is enabled */
126 /*****************************************************************************/
127 /* (W) SKCTL register values */
128 /*****************************************************************************/
130 #define SKCTL_KEYBOARD_DEBOUNCE 0x01 /* Enable keyboard debounce circuits */
131 #define SKCTL_KEYBOARD_SCANNING 0x02 /* Enable keyboard scanning circuit */
134 ** The pot scan counter completes its sequence in two TV line times instead of
135 ** one frame time (228 scan lines). Not as accurate as the normal pot scan
137 #define SKCTL_FAST_POT_SCAN 0x04
139 /* POKEY two-tone mode
140 ** Serial output is transmitted as a two-tone signal rather than a logic true/false.
142 #define SKCTL_TWO_TONE_MODE 0x08
144 /* Force break (serial output to zero) */
145 #define SKCTL_FORCE_BREAK 0x80
148 /* Bits 4, 5, and 6 of SKCTL set Serial Mode Control: */
150 /* Trans. & Receive rates set by external clock; Also internal clock phase reset to zero. */
151 #define SKCTL_SER_MODE_TX_EXT_RX_EXT 0x00
153 /* Trans. rate set by external clock; Receive asynch. (ch. 4) (CH3 and CH4). */
154 #define SKCTL_SER_MODE_TX_EXT_RX_ASYNC 0x10
156 /* Trans. & Receive rates set by Chan. 4; Chan. 4 output on Bi-Direct. clock line. */
157 #define SKCTL_SER_MODE_TX_CH4_RX_CH4_BIDIR 0x20
159 /* N.B.: Bit combination 0,1,1 not useful */
161 /* Trans. rate set by Chan. 4; Receive rate set by external clock. */
162 #define SKCTL_SER_MODE_TX_CH4_RX_EXT 0x40
164 /* N.B.: Bit combination 1,0,1 not useful */
166 /* Trans. rate set by Chan. 2; Receive rate set by Chan. 4; Chan. 4 out on Bi-Direct. clock line. */
167 #define SKCTL_SER_MODE_TX_CH2_RX_CH4_BIDIR 0x60
169 /* Trans. rate set by Chan. 2; Receive asynch. (chan 3 & 4); Bi-Direct. clock not used (tri-state condition). */
170 #define SKCTL_SER_MODE_TX_CH4_RX_ASYNC 0x70
173 /*****************************************************************************/
174 /* Define a structure with the POKEY register offsets for read (R) */
175 /*****************************************************************************/
177 struct __pokey_read {
178 unsigned char pot0; /* paddle 0 value */
179 unsigned char pot1; /* paddle 1 value */
180 unsigned char pot2; /* paddle 2 value */
181 unsigned char pot3; /* paddle 3 value */
182 unsigned char pot4; /* paddle 4 value */
183 unsigned char pot5; /* paddle 5 value */
184 unsigned char pot6; /* paddle 6 value */
185 unsigned char pot7; /* paddle 7 value */
186 unsigned char allpot; /* eight paddle port status (see "POTGO") */
187 unsigned char kbcode; /* keyboard code */
188 unsigned char random; /* random number generator */
189 unsigned char unuse2; /* unused */
190 unsigned char unuse3; /* unused */
191 unsigned char serin; /* serial port input */
192 unsigned char irqst; /* interrupt request status */
193 unsigned char skstat; /* serial port status */
197 /*****************************************************************************/
198 /* (R) SKSTAT register values */
199 /*****************************************************************************/
201 #define SKSTAT_SERIN_SHIFTREG_BUSY 0x02 /* Serial input shift register busy */
202 #define SKSTAT_LASTKEY_PRESSED 0x04 /* the last key is still pressed */
203 #define SKSTAT_SHIFTKEY_PRESSED 0x08 /* the [Shift] key is pressed */
204 #define SKSTAT_DATA_READ_INGORING_SHIFTREG 0x10 /* Data can be read directly from the serial input port, ignoring the shift register. */
205 #define SKSTAT_KEYBOARD_OVERRUN 0x20 /* Keyboard over-run; Reset BITs 7, 6 and 5 (latches) to 1, using SKREST */
206 #define SKSTAT_INPUT_OVERRUN 0x40 /* Serial data input over-run. Reset latches as above. */
207 #define SKSTAT_INPUT_FRAMEERROR 0x80 /* Serial data input frame error caused by missing or extra bits. Reset latches as above. */
210 /* KBCODE, internal keyboard codes for Atari 8-bit computers,
211 ** are #defined as "KEY_..." in "atari.h".
212 ** Note some keys are not read via KBCODE:
214 ** - Start, Select, and Option; see CONSOL in "gtia.h"
219 /* End of _pokey.h */
220 #endif /* #ifndef __POKEY_H */