3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _OMAP24XX_MEM_H_
26 #define _OMAP24XX_MEM_H_
28 #define SDRC_CS0_OSET 0x0
29 #define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
32 /* struct's for holding data tables for current boards, they are getting used
33 early in init when NO global access are there */
38 u32 sdrc_actim_ctrla_0;
39 u32 sdrc_actim_ctrlb_0;
45 } /*__attribute__ ((packed))*/;
46 typedef struct sdrc_data_s sdrc_data_t;
57 /* Slower full frequency range default timings for x32 operation*/
58 #define H4_2420_SDRC_SHARING 0x00000100
59 #define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
60 #define H4_2420_SDRC_MR_0_SDR 0x00000031
61 #define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
62 #define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
63 #define H4_2420_SDRC_MR_0_DDR 0x00000032
65 #ifndef CONFIG_OPTIMIZE_DDR
66 # define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909
67 # define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014
68 # define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401
69 # define H4_2420_SDRC_RFR_CTRL 0x0002da01
71 #define H4_2420_SDRC_DLLA_CTRL 0x00007307 /* load value at 100Mhz */
72 #define H4_2420_SDRC_DLLB_CTRL 0x00007307
74 #define H4_2422_SDRC_SHARING 0x00004b00
75 #define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
76 #ifndef CONFIG_OPTIMIZE_DDR
77 # define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909
78 # define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020
79 # define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401
80 # define H4_2422_SDRC_RFR_CTRL 0x0002da01
82 #define H4_2422_SDRC_MR_0_DDR 0x00000032
83 #define H4_2422_SDRC_DLLA_CTRL 0x00007307
84 #define H4_2422_SDRC_DLLB_CTRL 0x00007307
86 /* optimized timings */
87 #define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
88 #define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
89 #define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settigs */
90 #define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
91 #define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 /* this is not optimal yet */
92 #define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
94 #ifdef CONFIG_OPTIMIZE_DDR
95 # ifdef PRCM_CONFIG_II
96 # define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
97 # define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
98 # define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_100MHz
99 # define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
100 # elif PRCM_CONFIG_III
101 # define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
102 # define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
103 # define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_133MHz
104 # define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
106 # define H4_2422_SDRC_ACTIM_CTRLA_0 H4_2420_SDRC_ACTIM_CTRLA_0
107 # define H4_2422_SDRC_ACTIM_CTRLB_0 H4_2420_SDRC_ACTIM_CTRLB_0
108 # define H4_2422_SDRC_RFR_CTRL_ES1 H4_2420_SDRC_RFR_CTRL_ES1
109 # define H4_2422_SDRC_RFR_CTRL H4_2420_SDRC_RFR_CTRL
114 #ifdef PRCM_CONFIG_II /* L3 at 100MHz */
116 #define H4_24XX_GPMC_CONFIG1_0 0x0
117 #define H4_24XX_GPMC_CONFIG2_0 0x00141400
118 #define H4_24XX_GPMC_CONFIG3_0 0x00141400
119 #define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
120 #define H4_24XX_GPMC_CONFIG5_0 0x010C1414
121 #define H4_24XX_GPMC_CONFIG6_0 0x00000A80
123 #define H4_24XX_GPMC_CONFIG1_0 0x3
124 #define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
125 #define H4_24XX_GPMC_CONFIG3_0 0x00050502
126 #define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
127 #define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
129 #define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
131 #define H4_24XX_GPMC_CONFIG1_1 0x00011000
132 #define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
133 #define H4_24XX_GPMC_CONFIG3_1 0x00080802
134 #define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
135 #define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
136 #define H4_24XX_GPMC_CONFIG6_1 0x000003C2
137 #define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
140 #ifdef PRCM_CONFIG_III /* L3 at 133MHz */
142 #define H4_24XX_GPMC_CONFIG1_0 0x0
143 #define H4_24XX_GPMC_CONFIG2_0 0x00141400
144 #define H4_24XX_GPMC_CONFIG3_0 0x00141400
145 #define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
146 #define H4_24XX_GPMC_CONFIG5_0 0x010C1414
147 #define H4_24XX_GPMC_CONFIG6_0 0x00000A80
149 #define H4_24XX_GPMC_CONFIG1_0 0x3
150 #define H4_24XX_GPMC_CONFIG2_0 0x00151501
151 #define H4_24XX_GPMC_CONFIG3_0 0x00060602
152 #define H4_24XX_GPMC_CONFIG4_0 0x10081008
153 #define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
154 #define H4_24XX_GPMC_CONFIG6_0 0x000004c4
156 #define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
158 #define H4_24XX_GPMC_CONFIG1_1 0x00011000
159 #define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
160 #define H4_24XX_GPMC_CONFIG3_1 0x00080803
161 #define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
162 #define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
163 #define H4_24XX_GPMC_CONFIG6_1 0x000004C4
164 #define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
167 #ifdef CONFIG_APTIX /* SDRC-SDR for Aptix x16 */
168 #define VAL_H4_SDRC_SHARING_16 0x00002400 /* No-Tristate, 16bit on D31-D16, CS1=dont care */
169 #define VAL_H4_SDRC_SHARING 0x00000100
170 #define VAL_H4_SDRC_MCFG_0_16 0x00901000 /* SDR-SDRAM,External,x16 bit */
171 #define VAL_H4_SDRC_MCFG_0 0x01702011
172 #define VAL_H4_SDRC_MR_0 0x00000029 /* Burst=2, Serial Mode, CAS 3*/
173 #define VAL_H4_SDRC_RFR_CTRL_0 0x00001703 /* refresh time */
174 #define VAL_H4_SDRC_DCDL2_CTRL 0x5A59B485