2 * include/asm-armnommu/arch-netarm/netarm_mem_module.h
4 * Copyright (C) 2000, 2001 NETsilicon, Inc.
5 * Copyright (C) 2000, 2001 Red Hat, Inc.
7 * This software is copyrighted by Red Hat. LICENSEE agrees that
8 * it will not delete this copyright notice, trademarks or protective
9 * notices from any copy made by LICENSEE.
11 * This software is provided "AS-IS" and any express or implied
12 * warranties or conditions, including but not limited to any
13 * implied warranties of merchantability and fitness for a particular
14 * purpose regarding this software. In no event shall Red Hat
15 * be liable for any indirect, consequential, or incidental damages,
16 * loss of profits or revenue, loss of use or data, or interruption
17 * of business, whether the alleged damages are labeled in contract,
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * author(s) : Joe deBlaquiere
32 #ifndef __NETARM_MEM_MODULE_REGISTERS_H
33 #define __NETARM_MEM_MODULE_REGISTERS_H
35 /* GEN unit register offsets */
37 #define NETARM_MEM_MODULE_BASE (0xFFC00000)
39 #define NETARM_MEM_MODULE_CONFIG (0x00)
40 #define NETARM_MEM_CS0_BASE_ADDR (0x10)
41 #define NETARM_MEM_CS0_OPTIONS (0x14)
42 #define NETARM_MEM_CS1_BASE_ADDR (0x20)
43 #define NETARM_MEM_CS1_OPTIONS (0x24)
44 #define NETARM_MEM_CS2_BASE_ADDR (0x30)
45 #define NETARM_MEM_CS2_OPTIONS (0x34)
46 #define NETARM_MEM_CS3_BASE_ADDR (0x40)
47 #define NETARM_MEM_CS3_OPTIONS (0x44)
48 #define NETARM_MEM_CS4_BASE_ADDR (0x50)
49 #define NETARM_MEM_CS4_OPTIONS (0x54)
51 /* select bitfield defintions */
53 /* Module Configuration Register ( 0xFFC0_0000 ) */
55 #define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000)
56 #define NETARM_MEM_CFG_REFRESH_EN (0x00800000)
58 #define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000)
59 #define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000)
60 #define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000)
61 #define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000)
63 #define NETARM_MEM_CFG_PORTC_AMUX (0x00100000)
65 #define NETARM_MEM_CFG_A27_ADDR (0x00080000)
66 #define NETARM_MEM_CFG_A27_CS0OE (0x00000000)
68 #define NETARM_MEM_CFG_A26_ADDR (0x00040000)
69 #define NETARM_MEM_CFG_A26_CS0WE (0x00000000)
71 #define NETARM_MEM_CFG_A25_ADDR (0x00020000)
72 #define NETARM_MEM_CFG_A25_BLAST (0x00000000)
74 #define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000)
77 /* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
78 /* the expression will round down, so make sure to reverse it to verify */
79 /* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */
80 /* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
82 #define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
83 (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
87 /* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
88 /* the expression will round down, so make sure to reverse it toverify */
89 /* it is what you want. period = [( count + 1 ) * 4] / Fxtal */
91 #define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
92 (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
96 /* Base Address Registers (0xFFC0_00X0) */
98 #define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000)
100 /* macro to define base */
102 #define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
104 #define NETARM_MEM_BAR_DRAM_FP (0x00000000)
105 #define NETARM_MEM_BAR_DRAM_EDO (0x00000100)
106 #define NETARM_MEM_BAR_DRAM_SYNC (0x00000200)
108 #define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000)
109 #define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080)
111 #define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000)
112 #define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020)
114 #define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010)
116 #define NETARM_MEM_BAR_DRAM_SEL (0x00000008)
118 #define NETARM_MEM_BAR_BURST_EN (0x00000004)
120 #define NETARM_MEM_BAR_WRT_PROT (0x00000002)
122 #define NETARM_MEM_BAR_VALID (0x00000001)
124 /* Option Registers (0xFFC0_00X4) */
126 /* macro to define which bits of the base are significant */
128 #define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
130 #define NETARM_MEM_OPT_WAIT_MASK (0x00000F00)
132 #define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
134 #define NETARM_MEM_OPT_BCYC_1 (0x00000000)
135 #define NETARM_MEM_OPT_BCYC_2 (0x00000040)
136 #define NETARM_MEM_OPT_BCYC_3 (0x00000080)
137 #define NETARM_MEM_OPT_BCYC_4 (0x000000C0)
139 #define NETARM_MEM_OPT_BSIZE_2 (0x00000000)
140 #define NETARM_MEM_OPT_BSIZE_4 (0x00000010)
141 #define NETARM_MEM_OPT_BSIZE_8 (0x00000020)
142 #define NETARM_MEM_OPT_BSIZE_16 (0x00000030)
144 #define NETARM_MEM_OPT_32BIT (0x00000000)
145 #define NETARM_MEM_OPT_16BIT (0x00000004)
146 #define NETARM_MEM_OPT_8BIT (0x00000008)
147 #define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C)
149 #define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C)
151 #define NETARM_MEM_OPT_READ_ASYNC (0x00000000)
152 #define NETARM_MEM_OPT_READ_SYNC (0x00000002)
154 #define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000)
155 #define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)