2 * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #ifndef __ASM_ARCH_AT91_GPIO_H
14 #define __ASM_ARCH_AT91_GPIO_H
17 #include <asm/errno.h>
18 #include <asm/arch/at91_pio.h>
19 #include <asm/arch/hardware.h>
21 #ifdef CONFIG_AT91_LEGACY
25 #define MAX_GPIO_BANKS 5
27 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
29 #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
30 #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
31 #define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
32 #define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
33 #define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
34 #define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
35 #define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
36 #define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
37 #define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
38 #define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
39 #define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
40 #define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
41 #define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
42 #define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
43 #define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
44 #define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
45 #define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
46 #define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
47 #define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
48 #define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
49 #define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
50 #define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
51 #define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
52 #define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
53 #define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
54 #define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
55 #define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
56 #define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
57 #define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
58 #define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
59 #define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
60 #define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
62 #define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
63 #define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
64 #define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
65 #define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
66 #define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
67 #define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
68 #define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
69 #define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
70 #define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
71 #define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
72 #define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
73 #define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
74 #define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
75 #define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
76 #define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
77 #define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
78 #define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
79 #define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
80 #define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
81 #define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
82 #define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
83 #define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
84 #define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
85 #define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
86 #define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
87 #define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
88 #define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
89 #define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
90 #define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
91 #define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
92 #define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
93 #define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
95 #define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
96 #define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
97 #define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
98 #define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
99 #define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
100 #define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
101 #define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
102 #define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
103 #define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
104 #define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
105 #define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
106 #define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
107 #define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
108 #define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
109 #define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
110 #define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
111 #define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
112 #define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
113 #define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
114 #define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
115 #define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
116 #define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
117 #define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
118 #define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
119 #define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
120 #define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
121 #define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
122 #define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
123 #define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
124 #define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
125 #define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
126 #define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
128 #define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
129 #define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
130 #define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
131 #define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
132 #define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
133 #define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
134 #define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
135 #define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
136 #define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
137 #define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
138 #define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
139 #define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
140 #define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
141 #define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
142 #define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
143 #define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
144 #define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
145 #define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
146 #define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
147 #define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
148 #define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
149 #define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
150 #define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
151 #define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
152 #define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
153 #define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
154 #define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
155 #define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
156 #define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
157 #define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
158 #define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
159 #define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
161 #define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
162 #define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
163 #define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
164 #define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
165 #define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
166 #define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
167 #define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
168 #define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
169 #define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
170 #define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
171 #define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
172 #define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
173 #define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
174 #define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
175 #define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
176 #define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
177 #define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
178 #define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
179 #define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
180 #define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
181 #define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
182 #define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
183 #define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
184 #define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
185 #define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
186 #define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
187 #define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
188 #define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
189 #define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
190 #define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
191 #define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
192 #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
194 static unsigned long at91_pios[] = {
206 static inline void *pin_to_controller(unsigned pin)
210 return (void *)(AT91_BASE_SYS + at91_pios[pin]);
213 static inline unsigned pin_to_mask(unsigned pin)
216 return 1 << (pin % 32);
220 * mux the pin to the "GPIO" peripheral role.
222 static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
224 void *pio = pin_to_controller(pin);
225 unsigned mask = pin_to_mask(pin);
227 __raw_writel(mask, pio + PIO_IDR);
228 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
229 __raw_writel(mask, pio + PIO_PER);
234 * mux the pin to the "A" internal peripheral role.
236 static inline int at91_set_A_periph(unsigned pin, int use_pullup)
238 void *pio = pin_to_controller(pin);
239 unsigned mask = pin_to_mask(pin);
241 __raw_writel(mask, pio + PIO_IDR);
242 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
243 __raw_writel(mask, pio + PIO_ASR);
244 __raw_writel(mask, pio + PIO_PDR);
249 * mux the pin to the "B" internal peripheral role.
251 static inline int at91_set_B_periph(unsigned pin, int use_pullup)
253 void *pio = pin_to_controller(pin);
254 unsigned mask = pin_to_mask(pin);
256 __raw_writel(mask, pio + PIO_IDR);
257 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
258 __raw_writel(mask, pio + PIO_BSR);
259 __raw_writel(mask, pio + PIO_PDR);
264 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
265 * configure it for an input.
267 static inline int at91_set_gpio_input(unsigned pin, int use_pullup)
269 void *pio = pin_to_controller(pin);
270 unsigned mask = pin_to_mask(pin);
272 __raw_writel(mask, pio + PIO_IDR);
273 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
274 __raw_writel(mask, pio + PIO_ODR);
275 __raw_writel(mask, pio + PIO_PER);
280 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
281 * and configure it for an output.
283 static inline int at91_set_gpio_output(unsigned pin, int value)
285 void *pio = pin_to_controller(pin);
286 unsigned mask = pin_to_mask(pin);
288 __raw_writel(mask, pio + PIO_IDR);
289 __raw_writel(mask, pio + PIO_PUDR);
290 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
291 __raw_writel(mask, pio + PIO_OER);
292 __raw_writel(mask, pio + PIO_PER);
297 * enable/disable the glitch filter; mostly used with IRQ handling.
299 static inline int at91_set_deglitch(unsigned pin, int is_on)
301 void *pio = pin_to_controller(pin);
302 unsigned mask = pin_to_mask(pin);
304 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
309 * enable/disable the multi-driver; This is only valid for output and
310 * allows the output pin to run as an open collector output.
312 static inline int at91_set_multi_drive(unsigned pin, int is_on)
314 void *pio = pin_to_controller(pin);
315 unsigned mask = pin_to_mask(pin);
317 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
321 static inline int gpio_direction_input(unsigned pin)
323 void *pio = pin_to_controller(pin);
324 unsigned mask = pin_to_mask(pin);
326 if (!(__raw_readl(pio + PIO_PSR) & mask))
328 __raw_writel(mask, pio + PIO_ODR);
332 static inline int gpio_direction_output(unsigned pin, int value)
334 void *pio = pin_to_controller(pin);
335 unsigned mask = pin_to_mask(pin);
337 if (!(__raw_readl(pio + PIO_PSR) & mask))
339 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
340 __raw_writel(mask, pio + PIO_OER);
345 * assuming the pin is muxed as a gpio output, set its value.
347 static inline int at91_set_gpio_value(unsigned pin, int value)
349 void *pio = pin_to_controller(pin);
350 unsigned mask = pin_to_mask(pin);
352 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
357 * read the pin's value (works even if it's not muxed as a gpio).
359 static inline int at91_get_gpio_value(unsigned pin)
361 void *pio = pin_to_controller(pin);
362 unsigned mask = pin_to_mask(pin);
365 pdsr = __raw_readl(pio + PIO_PDSR);
366 return (pdsr & mask) != 0;