4 * Author : ATMEL AT91 application group
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 typedef volatile unsigned int AT91_REG;
30 /* Static Memory Controller */
31 typedef struct _AT91S_SMC {
32 AT91_REG SMC_SETUP0; /* Setup Register for CS 0 */
33 AT91_REG SMC_PULSE0; /* Pulse Register for CS 0 */
34 AT91_REG SMC_CYCLE0; /* Cycle Register for CS 0 */
35 AT91_REG SMC_CTRL0; /* Control Register for CS 0 */
36 AT91_REG SMC_SETUP1; /* Setup Register for CS 1 */
37 AT91_REG SMC_PULSE1; /* Pulse Register for CS 1 */
38 AT91_REG SMC_CYCLE1; /* Cycle Register for CS 1 */
39 AT91_REG SMC_CTRL1; /* Control Register for CS 1 */
40 AT91_REG SMC_SETUP2; /* Setup Register for CS 2 */
41 AT91_REG SMC_PULSE2; /* Pulse Register for CS 2 */
42 AT91_REG SMC_CYCLE2; /* Cycle Register for CS 2 */
43 AT91_REG SMC_CTRL2; /* Control Register for CS 2 */
44 AT91_REG SMC_SETUP3; /* Setup Register for CS 3 */
45 AT91_REG SMC_PULSE3; /* Pulse Register for CS 3 */
46 AT91_REG SMC_CYCLE3; /* Cycle Register for CS 3 */
47 AT91_REG SMC_CTRL3; /* Control Register for CS 3 */
48 AT91_REG SMC_SETUP4; /* Setup Register for CS 4 */
49 AT91_REG SMC_PULSE4; /* Pulse Register for CS 4 */
50 AT91_REG SMC_CYCLE4; /* Cycle Register for CS 4 */
51 AT91_REG SMC_CTRL4; /* Control Register for CS 4 */
52 AT91_REG SMC_SETUP5; /* Setup Register for CS 5 */
53 AT91_REG SMC_PULSE5; /* Pulse Register for CS 5 */
54 AT91_REG SMC_CYCLE5; /* Cycle Register for CS 5 */
55 AT91_REG SMC_CTRL5; /* Control Register for CS 5 */
56 AT91_REG SMC_SETUP6; /* Setup Register for CS 6 */
57 AT91_REG SMC_PULSE6; /* Pulse Register for CS 6 */
58 AT91_REG SMC_CYCLE6; /* Cycle Register for CS 6 */
59 AT91_REG SMC_CTRL6; /* Control Register for CS 6 */
60 AT91_REG SMC_SETUP7; /* Setup Register for CS 7 */
61 AT91_REG SMC_PULSE7; /* Pulse Register for CS 7 */
62 AT91_REG SMC_CYCLE7; /* Cycle Register for CS 7 */
63 AT91_REG SMC_CTRL7; /* Control Register for CS 7 */
64 } AT91S_SMC, *AT91PS_SMC;
66 /* SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x */
67 #define AT91C_SMC_NWESETUP (0x3F << 0) /* NWE Setup Length */
68 #define AT91C_SMC_NCSSETUPWR (0x3F << 8) /* NCS Setup Length for WRite */
69 #define AT91C_SMC_NRDSETUP (0x3F << 16) /* NRD Setup Length */
70 #define AT91C_SMC_NCSSETUPRD (0x3F << 24) /* NCS Setup Length for ReaD */
71 /* SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x */
72 #define AT91C_SMC_NWEPULSE (0x7F << 0) /* NWE Pulse Length */
73 #define AT91C_SMC_NCSPULSEWR (0x7F << 8) /* NCS Pulse Length for WRite */
74 #define AT91C_SMC_NRDPULSE (0x7F << 16) /* NRD Pulse Length */
75 #define AT91C_SMC_NCSPULSERD (0x7F << 24) /* NCS Pulse Length for ReaD */
76 /* SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x */
77 #define AT91C_SMC_NWECYCLE (0x1FF << 0) /* Total Write Cycle Length */
78 #define AT91C_SMC_NRDCYCLE (0x1FF << 16) /* Total Read Cycle Length */
79 /* SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x */
80 #define AT91C_SMC_READMODE (0x1 << 0) /* Read Mode */
81 #define AT91C_SMC_WRITEMODE (0x1 << 1) /* Write Mode */
82 #define AT91C_SMC_NWAITM (0x3 << 5) /* NWAIT Mode */
83 /* External NWAIT disabled */
84 #define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5)
85 /* External NWAIT enabled in frozen mode */
86 #define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5)
87 /* External NWAIT enabled in ready mode */
88 #define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5)
89 #define AT91C_SMC_BAT (0x1 << 8) /* Byte Access Type */
91 * Write controled by ncs, nbs0, nbs1, nbs2, nbs3.
92 * Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
94 #define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8)
96 * Write controled by ncs, nwe0, nwe1, nwe2, nwe3.
97 * Read controled by ncs and nrd.
99 #define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8)
100 #define AT91C_SMC_DBW (0x3 << 12) /* Data Bus Width */
101 #define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12)
102 #define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12)
103 #define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12)
104 #define AT91C_SMC_TDF (0xF << 16) /* Data Float Time */
105 #define AT91C_SMC_TDFEN (0x1 << 20) /* TDF Enabled */
106 #define AT91C_SMC_PMEN (0x1 << 24) /* Page Mode Enabled */
107 #define AT91C_SMC_PS (0x3 << 28) /* Page Size */
108 #define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28)
109 #define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28)
110 #define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28)
111 #define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28)
112 /* SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x */
113 /* SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x */
114 /* SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x */
115 /* SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x */
116 /* SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x */
117 /* SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x */
118 /* SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x */
119 /* SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x */
120 /* SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x */
121 /* SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x */
122 /* SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x */
123 /* SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x */
124 /* SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x */
125 /* SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x */
126 /* SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x */
127 /* SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x */
128 /* SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x */
129 /* SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x */
130 /* SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x */
131 /* SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x */
132 /* SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x */
133 /* SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x */
134 /* SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x */
135 /* SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x */
136 /* SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x */
137 /* SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x */
138 /* SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x */
139 /* SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x */
142 typedef struct _AT91S_CCFG {
143 AT91_REG Reserved0[1];
144 AT91_REG CCFG_MPBS0; /* MPB Slave 0 */
145 AT91_REG CCFG_UDPHS; /* AHB Periphs */
146 AT91_REG CCFG_MPBS1; /* MPB Slave 1 */
147 AT91_REG CCFG_EBICSA; /* EBI Chip Select Assignement */
148 AT91_REG Reserved1[2];
149 AT91_REG CCFG_MPBS2; /* MPB Slave 2 */
150 AT91_REG CCFG_MPBS3; /* MPB Slave 3 */
151 AT91_REG CCFG_BRIDGE; /* APB Bridge */
152 AT91_REG Reserved2[49];
153 AT91_REG CCFG_MATRIXVERSION;/* Version */
154 } AT91S_CCFG, *AT91PS_CCFG;
156 /* CCFG_UDPHS : (CCFG Offset: 0x8) UDPHS Configuration */
157 #define AT91C_CCFG_UDPHS_UDP_SELECT (0x1 << 31) /* UDPHS or UDP */
158 #define AT91C_CCFG_UDPHS_UDP_SELECT_UDPHS (0x0 << 31)
159 #define AT91C_CCFG_UDPHS_UDP_SELECT_UDP (0x1 << 31)
160 /* CCFG_EBICSA : (CCFG Offset: 0x10) EBI Chip Select Assignement Register */
161 #define AT91C_EBI_CS1A (0x1 << 1) /* CS1 Assignment */
162 #define AT91C_EBI_CS1A_SMC (0x0 << 1)
163 #define AT91C_EBI_CS1A_BCRAMC (0x1 << 1)
164 #define AT91C_EBI_CS3A (0x1 << 3) /* CS 3 Assignment */
165 #define AT91C_EBI_CS3A_SMC (0x0 << 3)
166 #define AT91C_EBI_CS3A_SM (0x1 << 3)
167 #define AT91C_EBI_CS4A (0x1 << 4) /* CS4 Assignment */
168 #define AT91C_EBI_CS4A_SMC (0x0 << 4)
169 #define AT91C_EBI_CS4A_CF (0x1 << 4)
170 #define AT91C_EBI_CS5A (0x1 << 5) /* CS 5 Assignment */
171 #define AT91C_EBI_CS5A_SMC (0x0 << 5)
172 #define AT91C_EBI_CS5A_CF (0x1 << 5)
173 #define AT91C_EBI_DBPUC (0x1 << 8) /* Data Bus Pull-up */
174 #define AT91C_EBI_DDRPUC (0x1 << 9) /* DDDR DQS Pull-up */
175 #define AT91C_EBI_SUP (0x1 << 16) /* EBI Supply */
176 #define AT91C_EBI_SUP_1V8 (0x0 << 16)
177 #define AT91C_EBI_SUP_3V3 (0x1 << 16)
178 #define AT91C_EBI_LP (0x1 << 17) /* EBI Low Power */
179 #define AT91C_EBI_LP_LOW_DRIVE (0x0 << 17)
180 #define AT91C_EBI_LP_STD_DRIVE (0x1 << 17)
181 #define AT91C_CCFG_DDR_SDR_SELECT (0x1 << 31) /* DDR or SDR */
182 #define AT91C_CCFG_DDR_SDR_SELECT_DDR (0x0 << 31)
183 #define AT91C_CCFG_DDR_SDR_SELECT_SDR (0x1 << 31)
184 /* CCFG_BRIDGE : (CCFG Offset: 0x24) BRIDGE Configuration */
185 #define AT91C_CCFG_AES_TDES_SELECT (0x1 << 31) /* AES or TDES */
186 #define AT91C_CCFG_AES_TDES_SELECT_AES (0x0 << 31)
187 #define AT91C_CCFG_AES_TDES_SELECT_TDES (0x1 << 31)
190 typedef struct _AT91S_PIO {
191 AT91_REG PIO_PER; /* PIO Enable Register */
192 AT91_REG PIO_PDR; /* PIO Disable Register */
193 AT91_REG PIO_PSR; /* PIO Status Register */
194 AT91_REG Reserved0[1];
195 AT91_REG PIO_OER; /* Output Enable Register */
196 AT91_REG PIO_ODR; /* Output Disable Register */
197 AT91_REG PIO_OSR; /* Output Status Register */
198 AT91_REG Reserved1[1];
199 AT91_REG PIO_IFER; /* Input Filter Enable Register */
200 AT91_REG PIO_IFDR; /* Input Filter Disable Register */
201 AT91_REG PIO_IFSR; /* Input Filter Status Register */
202 AT91_REG Reserved2[1];
203 AT91_REG PIO_SODR; /* Set Output Data Register */
204 AT91_REG PIO_CODR; /* Clear Output Data Register */
205 AT91_REG PIO_ODSR; /* Output Data Status Register */
206 AT91_REG PIO_PDSR; /* Pin Data Status Register */
207 AT91_REG PIO_IER; /* Interrupt Enable Register */
208 AT91_REG PIO_IDR; /* Interrupt Disable Register */
209 AT91_REG PIO_IMR; /* Interrupt Mask Register */
210 AT91_REG PIO_ISR; /* Interrupt Status Register */
211 AT91_REG PIO_MDER; /* Multi-driver Enable Register */
212 AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
213 AT91_REG PIO_MDSR; /* Multi-driver Status Register */
214 AT91_REG Reserved3[1];
215 AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
216 AT91_REG PIO_PPUER; /* Pull-up Enable Register */
217 AT91_REG PIO_PPUSR; /* Pull-up Status Register */
218 AT91_REG Reserved4[1];
219 AT91_REG PIO_ASR; /* Select A Register */
220 AT91_REG PIO_BSR; /* Select B Register */
221 AT91_REG PIO_ABSR; /* AB Select Status Register */
222 AT91_REG Reserved5[9];
223 AT91_REG PIO_OWER; /* Output Write Enable Register */
224 AT91_REG PIO_OWDR; /* Output Write Disable Register */
225 AT91_REG PIO_OWSR; /* Output Write Status Register */
226 } AT91S_PIO, *AT91PS_PIO;
228 /* Power Management Controller */
229 typedef struct _AT91S_PMC {
230 AT91_REG PMC_SCER; /* System Clock Enable Register */
231 AT91_REG PMC_SCDR; /* System Clock Disable Register */
232 AT91_REG PMC_SCSR; /* System Clock Status Register */
233 AT91_REG Reserved0[1];
234 AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
235 AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
236 AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
237 AT91_REG PMC_UCKR; /* UTMI Clock Configuration Register */
238 AT91_REG PMC_MOR; /* Main Oscillator Register */
239 AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
240 AT91_REG PMC_PLLAR; /* PLL A Register */
241 AT91_REG PMC_PLLBR; /* PLL B Register */
242 AT91_REG PMC_MCKR; /* Master Clock Register */
243 AT91_REG Reserved1[3];
244 AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
245 AT91_REG PMC_IER; /* Interrupt Enable Register */
246 AT91_REG PMC_IDR; /* Interrupt Disable Register */
247 AT91_REG PMC_SR; /* Status Register */
248 AT91_REG PMC_IMR; /* Interrupt Mask Register */
249 } AT91S_PMC, *AT91PS_PMC;
251 /* PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register */
252 #define AT91C_PMC_PCK (0x1 << 0) /* Processor Clock */
253 #define AT91C_PMC_OTG (0x1 << 5) /* USB OTG Clock */
254 #define AT91C_PMC_UHP (0x1 << 6) /* USB Host Port Clock */
255 #define AT91C_PMC_UDP (0x1 << 7) /* USB Device Port Clock */
256 #define AT91C_PMC_PCK0 (0x1 << 8) /* Programmable Clock Output */
257 #define AT91C_PMC_PCK1 (0x1 << 9) /* Programmable Clock Output */
258 #define AT91C_PMC_PCK2 (0x1 << 10) /* Programmable Clock Output */
259 #define AT91C_PMC_PCK3 (0x1 << 11) /* Programmable Clock Output */
260 /* PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register */
261 /* PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register */
262 /* CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register */
263 /* CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register */
264 /* CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register */
265 /* CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register */
266 /* CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register */
267 /* PMC_MCKR : (PMC Offset: 0x30) Master Clock Register */
268 #define AT91C_PMC_CSS (0x3 << 0) /* Clock Selection */
269 #define AT91C_PMC_CSS_SLOW_CLK (0x0 << 0) /* Slow Clk */
270 #define AT91C_PMC_CSS_MAIN_CLK (0x1 << 0) /* Main Clk */
271 #define AT91C_PMC_CSS_PLLA_CLK (0x2 << 0) /* PLL A Clk */
272 #define AT91C_PMC_CSS_PLLB_CLK (0x3 << 0) /* PLL B Clk */
273 #define AT91C_PMC_PRES (0x7 << 2) /* Clock Prescaler */
274 #define AT91C_PMC_PRES_CLK (0x0 << 2)
275 #define AT91C_PMC_PRES_CLK_2 (0x1 << 2)
276 #define AT91C_PMC_PRES_CLK_4 (0x2 << 2)
277 #define AT91C_PMC_PRES_CLK_8 (0x3 << 2)
278 #define AT91C_PMC_PRES_CLK_16 (0x4 << 2)
279 #define AT91C_PMC_PRES_CLK_32 (0x5 << 2)
280 #define AT91C_PMC_PRES_CLK_64 (0x6 << 2)
281 #define AT91C_PMC_MDIV (0x3 << 8) /* Master Clock Division */
282 #define AT91C_PMC_MDIV_1 (0x0 << 8)
283 #define AT91C_PMC_MDIV_2 (0x1 << 8)
284 #define AT91C_PMC_MDIV_4 (0x2 << 8)
285 /* PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register */
286 /* PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register */
287 #define AT91C_PMC_MOSCS (0x1 << 0) /* MOSC mask */
288 #define AT91C_PMC_LOCKA (0x1 << 1) /* PLL A mask */
289 #define AT91C_PMC_LOCKB (0x1 << 2) /* PLL B mask */
290 #define AT91C_PMC_MCKRDY (0x1 << 3) /* Master mask */
291 #define AT91C_PMC_LOCKU (0x1 << 6) /* PLL UTMI mask */
292 #define AT91C_PMC_PCK0RDY (0x1 << 8) /* PCK0_RDY mask */
293 #define AT91C_PMC_PCK1RDY (0x1 << 9) /* PCK1_RDY mask */
294 #define AT91C_PMC_PCK2RDY (0x1 << 10) /* PCK2_RDY mask */
295 #define AT91C_PMC_PCK3RDY (0x1 << 11) /* PCK3_RDY mask */
296 /* PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register */
297 /* PMC_SR : (PMC Offset: 0x68) PMC Status Register */
298 /* PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register */
300 /* Reset controller */
301 typedef struct _AT91S_RSTC {
302 AT91_REG RSTC_RCR; /* Reset Control Register */
303 AT91_REG RSTC_RSR; /* Reset Status Register */
304 AT91_REG RSTC_RMR; /* Reset Mode Register */
305 } AT91S_RSTC, *AT91PS_RSTC;
307 /* RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register */
308 #define AT91C_RSTC_PROCRST (0x1 << 0) /* Processor Reset */
309 #define AT91C_RSTC_ICERST (0x1 << 1) /* ICE Interface Reset */
310 #define AT91C_RSTC_PERRST (0x1 << 2) /* Peripheral Reset */
311 #define AT91C_RSTC_EXTRST (0x1 << 3) /* External Reset */
312 #define AT91C_RSTC_KEY (0xFF << 24) /* Password */
313 /* RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register */
314 #define AT91C_RSTC_URSTS (0x1 << 0) /* User Reset Status */
315 #define AT91C_RSTC_RSTTYP (0x7 << 8) /* Reset Type */
316 #define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8)
317 #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8)
318 #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8)
319 #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8)
320 #define AT91C_RSTC_RSTTYP_USER (0x4 << 8)
321 #define AT91C_RSTC_NRSTL (0x1 << 16) /* NRST pin level */
322 #define AT91C_RSTC_SRCMP (0x1 << 17) /* Software Rst in Progress. */
323 /* RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register */
324 #define AT91C_RSTC_URSTEN (0x1 << 0) /* User Reset Enable */
325 #define AT91C_RSTC_URSTIEN (0x1 << 4) /* User Reset Int. Enable */
326 #define AT91C_RSTC_ERSTL (0xF << 8) /* User Reset Enable */
328 /* Periodic Timer Controller */
329 typedef struct _AT91S_PITC {
330 AT91_REG PITC_PIMR; /* Period Interval Mode Register */
331 AT91_REG PITC_PISR; /* Period Interval Status Register */
332 AT91_REG PITC_PIVR; /* Period Interval Value Register */
333 AT91_REG PITC_PIIR; /* Period Interval Image Register */
334 } AT91S_PITC, *AT91PS_PITC;
336 /* PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register */
337 #define AT91C_PITC_PIV (0xFFFFF << 0) /* Periodic Interval Value */
338 #define AT91C_PITC_PITEN (0x1 << 24) /* PIT Enable */
339 #define AT91C_PITC_PITIEN (0x1 << 25) /* PIT Interrupt Enable */
340 /* PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register */
341 #define AT91C_PITC_PITS (0x1 << 0) /* PIT Status */
342 /* PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register */
343 #define AT91C_PITC_CPIV (0xFFFFF << 0) /* Current Value */
344 #define AT91C_PITC_PICNT (0xFFF << 20) /* Periodic Interval Counter */
345 /* PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register */
347 /* Serial Paraller Interface */
348 typedef struct _AT91S_SPI {
349 AT91_REG SPI_CR; /* Control Register */
350 AT91_REG SPI_MR; /* Mode Register */
351 AT91_REG SPI_RDR; /* Receive Data Register */
352 AT91_REG SPI_TDR; /* Transmit Data Register */
353 AT91_REG SPI_SR; /* Status Register */
354 AT91_REG SPI_IER; /* Interrupt Enable Register */
355 AT91_REG SPI_IDR; /* Interrupt Disable Register */
356 AT91_REG SPI_IMR; /* Interrupt Mask Register */
357 AT91_REG Reserved0[4];
358 AT91_REG SPI_CSR[4]; /* Chip Select Register */
359 AT91_REG Reserved1[48];
360 AT91_REG SPI_RPR; /* Receive Pointer Register */
361 AT91_REG SPI_RCR; /* Receive Counter Register */
362 AT91_REG SPI_TPR; /* Transmit Pointer Register */
363 AT91_REG SPI_TCR; /* Transmit Counter Register */
364 AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
365 AT91_REG SPI_RNCR; /* Receive Next Counter Register */
366 AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
367 AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
368 AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
369 AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
370 } AT91S_SPI, *AT91PS_SPI;
372 /* SPI_CR : (SPI Offset: 0x0) SPI Control Register */
373 #define AT91C_SPI_SPIEN (0x1 << 0) /* SPI Enable */
374 #define AT91C_SPI_SPIDIS (0x1 << 1) /* SPI Disable */
375 #define AT91C_SPI_SWRST (0x1 << 7) /* SPI Software reset */
376 #define AT91C_SPI_LASTXFER (0x1 << 24) /* SPI Last Transfer */
377 /* SPI_MR : (SPI Offset: 0x4) SPI Mode Register */
378 #define AT91C_SPI_MSTR (0x1 << 0) /* Master/Slave Mode */
379 #define AT91C_SPI_PS (0x1 << 1) /* Peripheral Select */
380 #define AT91C_SPI_PS_FIXED (0x0 << 1)
381 #define AT91C_SPI_PS_VARIABLE (0x1 << 1)
382 #define AT91C_SPI_PCSDEC (0x1 << 2) /* Chip Select Decode */
383 #define AT91C_SPI_FDIV (0x1 << 3) /* Clock Selection */
384 #define AT91C_SPI_MODFDIS (0x1 << 4) /* Mode Fault Detection */
385 #define AT91C_SPI_LLB (0x1 << 7) /* Clock Selection */
386 #define AT91C_SPI_PCS (0xF << 16) /* Peripheral Chip Select */
387 #define AT91C_SPI_DLYBCS (0xFF << 24) /* Delay Between Chip Selects */
388 /* SPI_RDR : (SPI Offset: 0x8) Receive Data Register */
389 #define AT91C_SPI_RD (0xFFFF << 0) /* Receive Data */
390 #define AT91C_SPI_RPCS (0xF << 16) /* Peripheral CS Status */
391 /* SPI_TDR : (SPI Offset: 0xc) Transmit Data Register */
392 #define AT91C_SPI_TD (0xFFFF << 0) /* Transmit Data */
393 #define AT91C_SPI_TPCS (0xF << 16) /* Peripheral CS Status */
394 /* SPI_SR : (SPI Offset: 0x10) Status Register */
395 #define AT91C_SPI_RDRF (0x1 << 0) /* Receive Data Register Full */
396 #define AT91C_SPI_TDRE (0x1 << 1) /* Trans. Data Register Empty */
397 #define AT91C_SPI_MODF (0x1 << 2) /* Mode Fault Error */
398 #define AT91C_SPI_OVRES (0x1 << 3) /* Overrun Error Status */
399 #define AT91C_SPI_ENDRX (0x1 << 4) /* End of Receiver Transfer */
400 #define AT91C_SPI_ENDTX (0x1 << 5) /* End of Receiver Transfer */
401 #define AT91C_SPI_RXBUFF (0x1 << 6) /* RXBUFF Interrupt */
402 #define AT91C_SPI_TXBUFE (0x1 << 7) /* TXBUFE Interrupt */
403 #define AT91C_SPI_NSSR (0x1 << 8) /* NSSR Interrupt */
404 #define AT91C_SPI_TXEMPTY (0x1 << 9) /* TXEMPTY Interrupt */
405 #define AT91C_SPI_SPIENS (0x1 << 16) /* Enable Status */
406 /* SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register */
407 /* SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register */
408 /* SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register */
409 /* SPI_CSR : (SPI Offset: 0x30) Chip Select Register */
410 #define AT91C_SPI_CPOL (0x1 << 0) /* Clock Polarity */
411 #define AT91C_SPI_NCPHA (0x1 << 1) /* Clock Phase */
412 #define AT91C_SPI_CSAAT (0x1 << 3) /* CS Active After Transfer */
413 #define AT91C_SPI_BITS (0xF << 4) /* Bits Per Transfer */
414 #define AT91C_SPI_BITS_8 (0x0 << 4) /* 8 Bits */
415 #define AT91C_SPI_BITS_9 (0x1 << 4) /* 9 Bits */
416 #define AT91C_SPI_BITS_10 (0x2 << 4) /* 10 Bits */
417 #define AT91C_SPI_BITS_11 (0x3 << 4) /* 11 Bits */
418 #define AT91C_SPI_BITS_12 (0x4 << 4) /* 12 Bits */
419 #define AT91C_SPI_BITS_13 (0x5 << 4) /* 13 Bits */
420 #define AT91C_SPI_BITS_14 (0x6 << 4) /* 14 Bits */
421 #define AT91C_SPI_BITS_15 (0x7 << 4) /* 15 Bits */
422 #define AT91C_SPI_BITS_16 (0x8 << 4) /* 16 Bits */
423 #define AT91C_SPI_SCBR (0xFF << 8) /* Serial Clock Baud Rate */
424 #define AT91C_SPI_DLYBS (0xFF << 16) /* Delay Before SPCK */
425 #define AT91C_SPI_DLYBCT (0xFF << 24) /* Delay Between Transfers */
426 /* SPI_PTCR : PDC Transfer Control Register */
427 #define AT91C_PDC_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
428 #define AT91C_PDC_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
429 #define AT91C_PDC_TXTEN (0x1 << 8) /* Transm. Transfer Enable */
430 #define AT91C_PDC_TXTDIS (0x1 << 9) /* Transm. Transfer Disable */
432 /* PIO definitions */
433 #define AT91C_PIO_PA0 (1 << 0) /* Pin Controlled by PA0 */
434 #define AT91C_PA0_SPI0_MISO AT91C_PIO_PA0
435 #define AT91C_PIO_PA1 (1 << 1) /* Pin Controlled by PA1 */
436 #define AT91C_PA1_SPI0_MOSI AT91C_PIO_PA1
437 #define AT91C_PIO_PA2 (1 << 2) /* Pin Controlled by PA2 */
438 #define AT91C_PA2_SPI0_SPCK AT91C_PIO_PA2
439 #define AT91C_PIO_PA3 (1 << 3) /* Pin Controlled by PA3 */
440 #define AT91C_PA3_SPI0_NPCS1 AT91C_PIO_PA3
441 #define AT91C_PIO_PA4 (1 << 4) /* Pin Controlled by PA4 */
442 #define AT91C_PA4_SPI0_NPCS2A AT91C_PIO_PA4
443 #define AT91C_PIO_PA5 (1 << 5) /* Pin Controlled by PA5 */
444 #define AT91C_PA5_SPI0_NPCS0 AT91C_PIO_PA5
445 #define AT91C_PIO_PA10 (1 << 10) /* Pin Controlled by PA10 */
446 #define AT91C_PIO_PA11 (1 << 11) /* Pin Controlled by PA11 */
447 #define AT91C_PIO_PA22 (1 << 22) /* Pin Controlled by PA22 */
448 #define AT91C_PA22_TXD0 AT91C_PIO_PA22
449 #define AT91C_PIO_PA23 (1 << 23) /* Pin Controlled by PA23 */
450 #define AT91C_PA23_RXD0 AT91C_PIO_PA23
451 #define AT91C_PIO_PA28 (1 << 28) /* Pin Controlled by PA28 */
452 #define AT91C_PA28_SPI0_NPCS3A AT91C_PIO_PA28
453 #define AT91C_PIO_PB21 (1 << 21) /* Pin Controlled by PB21 */
454 #define AT91C_PB21_E_TXCK AT91C_PIO_PB21
455 #define AT91C_PIO_PB22 (1 << 22) /* Pin Controlled by PB22 */
456 #define AT91C_PB22_E_RXDV AT91C_PIO_PB22
457 #define AT91C_PIO_PB23 (1 << 23) /* Pin Controlled by PB23 */
458 #define AT91C_PB23_E_TX0 AT91C_PIO_PB23
459 #define AT91C_PIO_PB24 (1 << 24) /* Pin Controlled by PB24 */
460 #define AT91C_PB24_E_TX1 AT91C_PIO_PB24
461 #define AT91C_PIO_PB25 (1 << 25) /* Pin Controlled by PB25 */
462 #define AT91C_PB25_E_RX0 AT91C_PIO_PB25
463 #define AT91C_PIO_PB26 (1 << 26) /* Pin Controlled by PB26 */
464 #define AT91C_PB26_E_RX1 AT91C_PIO_PB26
465 #define AT91C_PIO_PB27 (1 << 27) /* Pin Controlled by PB27 */
466 #define AT91C_PB27_E_RXER AT91C_PIO_PB27
467 #define AT91C_PIO_PB28 (1 << 28) /* Pin Controlled by PB28 */
468 #define AT91C_PB28_E_TXEN AT91C_PIO_PB28
469 #define AT91C_PIO_PB29 (1 << 29) /* Pin Controlled by PB29 */
470 #define AT91C_PB29_E_MDC AT91C_PIO_PB29
471 #define AT91C_PIO_PB30 (1 << 30) /* Pin Controlled by PB30 */
472 #define AT91C_PB30_E_MDIO AT91C_PIO_PB30
473 #define AT91C_PIO_PB31 (1 << 31) /* Pin Controlled by PB31 */
474 #define AT91C_PIO_PC29 (1 << 29) /* Pin Controlled by PC29 */
475 #define AT91C_PIO_PC30 (1 << 30) /* Pin Controlled by PC30 */
476 #define AT91C_PC30_DRXD AT91C_PIO_PC30
477 #define AT91C_PIO_PC31 (1 << 31) /* Pin Controlled by PC31 */
478 #define AT91C_PC31_DTXD AT91C_PIO_PC31
479 #define AT91C_PIO_PD0 (1 << 0) /* Pin Controlled by PD0 */
480 #define AT91C_PD0_TXD1 AT91C_PIO_PD0
481 #define AT91C_PD0_SPI0_NPCS2D AT91C_PIO_PD0
482 #define AT91C_PIO_PD1 (1 << 1) /* Pin Controlled by PD1 */
483 #define AT91C_PD1_RXD1 AT91C_PIO_PD1
484 #define AT91C_PD1_SPI0_NPCS3D AT91C_PIO_PD1
485 #define AT91C_PIO_PD2 (1 << 2) /* Pin Controlled by PD2 */
486 #define AT91C_PD2_TXD2 AT91C_PIO_PD2
487 #define AT91C_PIO_PD3 (1 << 3) /* Pin Controlled by PD3 */
488 #define AT91C_PD3_RXD2 AT91C_PIO_PD3
489 #define AT91C_PIO_PD15 (1 << 15) /* Pin Controlled by PD15 */
492 #define AT91C_ID_SYS 1 /* System Controller */
493 #define AT91C_ID_PIOABCD 2 /* Parallel IO Controller A, B, C, D */
494 #define AT91C_ID_US0 8 /* USART 0 */
495 #define AT91C_ID_US1 9 /* USART 1 */
496 #define AT91C_ID_US2 10 /* USART 2 */
497 #define AT91C_ID_SPI0 15 /* Serial Peripheral Interface 0 */
498 #define AT91C_ID_EMAC 22 /* Ethernet Mac */
499 #define AT91C_ID_UHP 29 /* USB Host Port */
502 #define AT91C_BASE_SMC ((AT91PS_SMC) 0xFFFFE800) /* SMC */
503 #define AT91C_BASE_CCFG ((AT91PS_CCFG) 0xFFFFEB10) /* CCFG */
504 #define AT91C_BASE_DBGU ((unsigned long)0xFFFFEE00) /* DBGU */
505 #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF200) /* PIOA */
506 #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF400) /* PIOB */
507 #define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF600) /* PIOC */
508 #define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFF800) /* PIOD */
509 #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* PMC */
510 #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) /* RSTC */
511 #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) /* PITC */
512 #define AT91C_BASE_US0 ((unsigned long)0xFFF8C000) /* US0 */
513 #define AT91C_BASE_US1 ((unsigned long)0xFFF90000) /* US1 */
514 #define AT91C_BASE_US2 ((unsigned long)0xFFF94000) /* US2 */
515 #define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFA4000) /* SPI0 */
516 #define AT91C_BASE_MACB ((unsigned long)0xFFFBC000) /* MACB */
projects / u-boot / blob