3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __ASM_ARCH_MX31_REGS_H
25 #define __ASM_ARCH_MX31_REGS_H
27 #define __REG(x) (*((volatile u32 *)(x)))
28 #define __REG16(x) (*((volatile u16 *)(x)))
29 #define __REG8(x) (*((volatile u8 *)(x)))
31 #define CCM_BASE 0x53f80000
32 #define CCM_CCMR (CCM_BASE + 0x00)
33 #define CCM_PDR0 (CCM_BASE + 0x04)
34 #define CCM_PDR1 (CCM_BASE + 0x08)
35 #define CCM_RCSR (CCM_BASE + 0x0c)
36 #define CCM_MPCTL (CCM_BASE + 0x10)
37 #define CCM_UPCTL (CCM_BASE + 0x14)
38 #define CCM_SPCTL (CCM_BASE + 0x18)
39 #define CCM_COSR (CCM_BASE + 0x1C)
40 #define CCM_CGR0 (CCM_BASE + 0x20)
41 #define CCM_CGR1 (CCM_BASE + 0x24)
42 #define CCM_CGR2 (CCM_BASE + 0x28)
44 #define CCMR_MDS (1 << 7)
45 #define CCMR_SBYCS (1 << 4)
46 #define CCMR_MPE (1 << 3)
47 #define CCMR_PRCS_MASK (3 << 1)
48 #define CCMR_FPM (1 << 1)
49 #define CCMR_CKIH (2 << 1)
51 #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
52 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
53 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
54 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
55 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
56 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
57 #define PDR0_MCU_PODF(x) ((x) & 0x7)
59 #define PLL_PD(x) (((x) & 0xf) << 26)
60 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
61 #define PLL_MFI(x) (((x) & 0xf) << 10)
62 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
64 #define WEIM_BASE 0xb8002000
65 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
66 #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
67 #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
69 #define IOMUXC_BASE 0x43FAC000
70 #define IOMUXC_GPR (IOMUXC_BASE + 0x8)
71 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
72 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
74 #define IPU_BASE 0x53fc0000
75 #define IPU_CONF IPU_BASE
77 #define IPU_CONF_PXL_ENDIAN (1<<8)
78 #define IPU_CONF_DU_EN (1<<7)
79 #define IPU_CONF_DI_EN (1<<6)
80 #define IPU_CONF_ADC_EN (1<<5)
81 #define IPU_CONF_SDC_EN (1<<4)
82 #define IPU_CONF_PF_EN (1<<3)
83 #define IPU_CONF_ROT_EN (1<<2)
84 #define IPU_CONF_IC_EN (1<<1)
85 #define IPU_CONF_SCI_EN (1<<0)
87 #define ARM_PPMRR 0x40000015
89 #define WDOG_BASE 0x53FDC000
94 #define GPIO1_BASE 0x53FCC000
95 #define GPIO2_BASE 0x53FD0000
96 #define GPIO3_BASE 0x53FA4000
97 #define GPIO_DR 0x00000000 /* data register */
98 #define GPIO_GDIR 0x00000004 /* direction register */
99 #define GPIO_PSR 0x00000008 /* pad status register */
102 * Signal Multiplexing (IOMUX)
105 /* bits in the SW_MUX_CTL registers */
106 #define MUX_CTL_OUT_GPIO_DR (0 << 4)
107 #define MUX_CTL_OUT_FUNC (1 << 4)
108 #define MUX_CTL_OUT_ALT1 (2 << 4)
109 #define MUX_CTL_OUT_ALT2 (3 << 4)
110 #define MUX_CTL_OUT_ALT3 (4 << 4)
111 #define MUX_CTL_OUT_ALT4 (5 << 4)
112 #define MUX_CTL_OUT_ALT5 (6 << 4)
113 #define MUX_CTL_OUT_ALT6 (7 << 4)
114 #define MUX_CTL_IN_NONE (0 << 0)
115 #define MUX_CTL_IN_GPIO (1 << 0)
116 #define MUX_CTL_IN_FUNC (2 << 0)
117 #define MUX_CTL_IN_ALT1 (4 << 0)
118 #define MUX_CTL_IN_ALT2 (8 << 0)
120 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
121 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
122 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
123 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
125 /* Register offsets based on IOMUXC_BASE */
127 #define MUX_CTL_RTS1 0x7c
128 #define MUX_CTL_CTS1 0x7d
129 #define MUX_CTL_DTR_DCE1 0x7e
130 #define MUX_CTL_DSR_DCE1 0x7f
131 #define MUX_CTL_CSPI2_SCLK 0x80
132 #define MUX_CTL_CSPI2_SPI_RDY 0x81
133 #define MUX_CTL_RXD1 0x82
134 #define MUX_CTL_TXD1 0x83
135 #define MUX_CTL_CSPI2_MISO 0x84
136 #define MUX_CTL_CSPI2_SS0 0x85
137 #define MUX_CTL_CSPI2_SS1 0x86
138 #define MUX_CTL_CSPI2_SS2 0x87
139 #define MUX_CTL_CSPI1_SS2 0x88
140 #define MUX_CTL_CSPI1_SCLK 0x89
141 #define MUX_CTL_CSPI1_SPI_RDY 0x8a
142 #define MUX_CTL_CSPI2_MOSI 0x8b
143 #define MUX_CTL_CSPI1_MOSI 0x8c
144 #define MUX_CTL_CSPI1_MISO 0x8d
145 #define MUX_CTL_CSPI1_SS0 0x8e
146 #define MUX_CTL_CSPI1_SS1 0x8f
149 * Helper macros for the MUX_[contact name]__[pin function] macros
151 #define IOMUX_MODE_POS 9
152 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
155 * These macros can be used in mx31_gpio_mux() and have the form
156 * MUX_[contact name]__[pin function]
158 #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
159 #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
160 #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
161 #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
163 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
164 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
165 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
166 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
167 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
168 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
169 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
170 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
172 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
173 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
174 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
175 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
176 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
177 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
178 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
179 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
181 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
182 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
185 * Memory regions and CS
187 #define IPU_MEM_BASE 0x70000000
188 #define CSD0_BASE 0x80000000
189 #define CSD1_BASE 0x90000000
190 #define CS0_BASE 0xA0000000
191 #define CS1_BASE 0xA8000000
192 #define CS2_BASE 0xB0000000
193 #define CS3_BASE 0xB2000000
194 #define CS4_BASE 0xB4000000
195 #define CS4_PSRAM_BASE 0xB5000000
196 #define CS5_BASE 0xB6000000
197 #define PCMCIA_MEM_BASE 0xC0000000
202 #define NFC_BASE_ADDR 0xB8000000
204 #endif /* __ASM_ARCH_MX31_REGS_H */