2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* Register offsets of common modules */
32 unsigned char res1[0xC0];
33 unsigned short gpmc_nadv_ale; /* 0xC0 */
34 unsigned short gpmc_noe; /* 0xC2 */
35 unsigned short gpmc_nwe; /* 0xC4 */
36 unsigned char res2[0x22A];
37 unsigned int status; /* 0x2F0 */
38 unsigned int gpstatus; /* 0x2F4 */
39 unsigned char res3[0x08];
40 unsigned int rpubkey_0; /* 0x300 */
41 unsigned int rpubkey_1; /* 0x304 */
42 unsigned int rpubkey_2; /* 0x308 */
43 unsigned int rpubkey_3; /* 0x30C */
44 unsigned int rpubkey_4; /* 0x310 */
45 unsigned char res4[0x04];
46 unsigned int randkey_0; /* 0x318 */
47 unsigned int randkey_1; /* 0x31C */
48 unsigned int randkey_2; /* 0x320 */
49 unsigned int randkey_3; /* 0x324 */
50 unsigned char res5[0x124];
51 unsigned int ctrl_omap_stat; /* 0x44C */
53 #else /* __ASSEMBLY__ */
54 #define CONTROL_STATUS 0x2F0
55 #endif /* __ASSEMBLY__ */
58 #define OMAP3503 0x5c00
59 #define OMAP3515 0x1c00
60 #define OMAP3525 0x4c00
61 #define OMAP3530 0x0c00
65 unsigned char res1[0x4];
66 unsigned int idcode; /* 0x04 */
67 unsigned int prod_id; /* 0x08 */
68 unsigned char res2[0x0C];
69 unsigned int die_id_0; /* 0x18 */
70 unsigned int die_id_1; /* 0x1C */
71 unsigned int die_id_2; /* 0x20 */
72 unsigned int die_id_3; /* 0x24 */
74 #endif /* __ASSEMBLY__ */
77 #define DEVICE_MASK (0x7 << 8)
78 #define SYSBOOT_MASK 0x1F
79 #define TST_DEVICE 0x0
80 #define EMU_DEVICE 0x1
84 #define GPMC_BASE (OMAP34XX_GPMC_BASE)
85 #define GPMC_CONFIG_CS0 0x60
89 unsigned int config1; /* 0x00 */
90 unsigned int config2; /* 0x04 */
91 unsigned int config3; /* 0x08 */
92 unsigned int config4; /* 0x0C */
93 unsigned int config5; /* 0x10 */
94 unsigned int config6; /* 0x14 */
95 unsigned int config7; /* 0x18 */
96 unsigned int nand_cmd; /* 0x1C */
97 unsigned int nand_adr; /* 0x20 */
98 unsigned int nand_dat; /* 0x24 */
99 unsigned char res[8]; /* blow up to 0x30 byte */
103 unsigned char res1[0x10];
104 unsigned int sysconfig; /* 0x10 */
105 unsigned char res2[0x4];
106 unsigned int irqstatus; /* 0x18 */
107 unsigned int irqenable; /* 0x1C */
108 unsigned char res3[0x20];
109 unsigned int timeout_control; /* 0x40 */
110 unsigned char res4[0xC];
111 unsigned int config; /* 0x50 */
112 unsigned int status; /* 0x54 */
113 unsigned char res5[0x8];
114 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
115 unsigned char res6[0x18];
116 unsigned int ecc_config; /* 0x1F4 */
117 unsigned int ecc_control; /* 0x1F8 */
118 unsigned int ecc_size_config; /* 0x1FC */
119 unsigned int ecc1_result; /* 0x200 */
120 unsigned int ecc2_result; /* 0x204 */
121 unsigned int ecc3_result; /* 0x208 */
122 unsigned int ecc4_result; /* 0x20C */
123 unsigned int ecc5_result; /* 0x210 */
124 unsigned int ecc6_result; /* 0x214 */
125 unsigned int ecc7_result; /* 0x218 */
126 unsigned int ecc8_result; /* 0x21C */
127 unsigned int ecc9_result; /* 0x220 */
129 #else /* __ASSEMBLY__ */
130 #define GPMC_CONFIG1 0x00
131 #define GPMC_CONFIG2 0x04
132 #define GPMC_CONFIG3 0x08
133 #define GPMC_CONFIG4 0x0C
134 #define GPMC_CONFIG5 0x10
135 #define GPMC_CONFIG6 0x14
136 #define GPMC_CONFIG7 0x18
137 #endif /* __ASSEMBLY__ */
140 #define FLASH_BASE 0x10000000 /* NOR flash, */
141 /* aligned to 256 Meg */
142 #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
143 /* aligned to 64 Meg */
144 #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
145 /* aligned to 256 Meg */
146 #define DEBUG_BASE 0x08000000 /* debug board */
147 #define NAND_BASE 0x30000000 /* NAND addr */
148 /* (actual size small port) */
149 #define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
150 #define ONENAND_MAP 0x20000000 /* OneNand addr */
151 /* (actual size small port) */
155 unsigned char res1[0x10];
156 unsigned int sysconfig; /* 0x10 */
157 unsigned char res2[0x34];
158 unsigned int rg_att0; /* 0x48 */
159 unsigned char res3[0x84];
160 unsigned int class_arb0; /* 0xD0 */
162 #endif /* __ASSEMBLY__ */
164 #define BURSTCOMPLETE_GROUP7 (0x1 << 31)
169 unsigned int mcfg; /* 0x80 || 0xB0 */
170 unsigned int mr; /* 0x84 || 0xB4 */
171 unsigned char res1[0x4];
172 unsigned int emr2; /* 0x8C || 0xBC */
173 unsigned char res2[0x14];
174 unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
175 unsigned int manual; /* 0xA8 || 0xD8 */
176 unsigned char res3[0x4];
180 unsigned int ctrla; /* 0x9C || 0xC4 */
181 unsigned int ctrlb; /* 0xA0 || 0xC8 */
185 unsigned char res1[0x10];
186 unsigned int sysconfig; /* 0x10 */
187 unsigned int status; /* 0x14 */
188 unsigned char res2[0x28];
189 unsigned int cs_cfg; /* 0x40 */
190 unsigned int sharing; /* 0x44 */
191 unsigned char res3[0x18];
192 unsigned int dlla_ctrl; /* 0x60 */
193 unsigned int dlla_status; /* 0x64 */
194 unsigned int dllb_ctrl; /* 0x68 */
195 unsigned int dllb_status; /* 0x6C */
196 unsigned int power; /* 0x70 */
197 unsigned char res4[0xC];
198 struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
200 #endif /* __ASSEMBLY__ */
202 #define DLLPHASE_90 (0x1 << 1)
203 #define LOADDLL (0x1 << 2)
204 #define ENADLL (0x1 << 3)
205 #define DLL_DELAY_MASK 0xFF00
206 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
208 #define PAGEPOLICY_HIGH (0x1 << 0)
209 #define SRFRONRESET (0x1 << 7)
210 #define WAKEUPPROC (0x1 << 26)
212 #define DDR_SDRAM (0x1 << 0)
213 #define DEEPPD (0x1 << 3)
214 #define B32NOT16 (0x1 << 4)
215 #define BANKALLOCATION (0x2 << 6)
216 #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
217 #define ADDRMUXLEGACY (0x1 << 19)
218 #define CASWIDTH_10BITS (0x5 << 20)
219 #define RASWIDTH_13BITS (0x2 << 24)
220 #define BURSTLENGTH4 (0x2 << 0)
221 #define CASL3 (0x3 << 4)
222 #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
223 #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
224 #define ARE_ARCV_1 (0x1 << 0)
225 #define ARCV (0x4e2 << 8) /* Autorefresh count */
226 #define OMAP34XX_SDRC_CS0 0x80000000
227 #define OMAP34XX_SDRC_CS1 0xA0000000
229 #define CMD_PRECHARGE 0x1
230 #define CMD_AUTOREFRESH 0x2
231 #define CMD_ENTR_PWRDOWN 0x3
232 #define CMD_EXIT_PWRDOWN 0x4
233 #define CMD_ENTR_SRFRSH 0x5
234 #define CMD_CKE_HIGH 0x6
235 #define CMD_CKE_LOW 0x7
236 #define SOFTRESET (0x1 << 1)
237 #define SMART_IDLE (0x2 << 3)
238 #define REF_ON_IDLE (0x1 << 6)
240 /* timer regs offsets (32 bit regs) */
244 unsigned int tidr; /* 0x00 r */
245 unsigned char res[0xc];
246 unsigned int tiocp_cfg; /* 0x10 rw */
247 unsigned int tistat; /* 0x14 r */
248 unsigned int tisr; /* 0x18 rw */
249 unsigned int tier; /* 0x1c rw */
250 unsigned int twer; /* 0x20 rw */
251 unsigned int tclr; /* 0x24 rw */
252 unsigned int tcrr; /* 0x28 rw */
253 unsigned int tldr; /* 0x2c rw */
254 unsigned int ttgr; /* 0x30 rw */
255 unsigned int twpc; /* 0x34 r*/
256 unsigned int tmar; /* 0x38 rw*/
257 unsigned int tcar1; /* 0x3c r */
258 unsigned int tcicr; /* 0x40 rw */
259 unsigned int tcar2; /* 0x44 r */
261 #endif /* __ASSEMBLY__ */
263 /* enable sys_clk NO-prescale /1 */
264 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
269 unsigned char res1[0x34];
270 unsigned int wwps; /* 0x34 r */
271 unsigned char res2[0x10];
272 unsigned int wspr; /* 0x48 rw */
274 #endif /* __ASSEMBLY__ */
276 #define WD_UNLOCK1 0xAAAA
277 #define WD_UNLOCK2 0x5555
280 #define PRCM_BASE 0x48004000
284 unsigned int fclken_iva2; /* 0x00 */
285 unsigned int clken_pll_iva2; /* 0x04 */
286 unsigned char res1[0x1c];
287 unsigned int idlest_pll_iva2; /* 0x24 */
288 unsigned char res2[0x18];
289 unsigned int clksel1_pll_iva2 ; /* 0x40 */
290 unsigned int clksel2_pll_iva2; /* 0x44 */
291 unsigned char res3[0x8bc];
292 unsigned int clken_pll_mpu; /* 0x904 */
293 unsigned char res4[0x1c];
294 unsigned int idlest_pll_mpu; /* 0x924 */
295 unsigned char res5[0x18];
296 unsigned int clksel1_pll_mpu; /* 0x940 */
297 unsigned int clksel2_pll_mpu; /* 0x944 */
298 unsigned char res6[0xb8];
299 unsigned int fclken1_core; /* 0xa00 */
300 unsigned char res7[0xc];
301 unsigned int iclken1_core; /* 0xa10 */
302 unsigned int iclken2_core; /* 0xa14 */
303 unsigned char res8[0x28];
304 unsigned int clksel_core; /* 0xa40 */
305 unsigned char res9[0xbc];
306 unsigned int fclken_gfx; /* 0xb00 */
307 unsigned char res10[0xc];
308 unsigned int iclken_gfx; /* 0xb10 */
309 unsigned char res11[0x2c];
310 unsigned int clksel_gfx; /* 0xb40 */
311 unsigned char res12[0xbc];
312 unsigned int fclken_wkup; /* 0xc00 */
313 unsigned char res13[0xc];
314 unsigned int iclken_wkup; /* 0xc10 */
315 unsigned char res14[0xc];
316 unsigned int idlest_wkup; /* 0xc20 */
317 unsigned char res15[0x1c];
318 unsigned int clksel_wkup; /* 0xc40 */
319 unsigned char res16[0xbc];
320 unsigned int clken_pll; /* 0xd00 */
321 unsigned char res17[0x1c];
322 unsigned int idlest_ckgen; /* 0xd20 */
323 unsigned char res18[0x1c];
324 unsigned int clksel1_pll; /* 0xd40 */
325 unsigned int clksel2_pll; /* 0xd44 */
326 unsigned int clksel3_pll; /* 0xd48 */
327 unsigned char res19[0xb4];
328 unsigned int fclken_dss; /* 0xe00 */
329 unsigned char res20[0xc];
330 unsigned int iclken_dss; /* 0xe10 */
331 unsigned char res21[0x2c];
332 unsigned int clksel_dss; /* 0xe40 */
333 unsigned char res22[0xbc];
334 unsigned int fclken_cam; /* 0xf00 */
335 unsigned char res23[0xc];
336 unsigned int iclken_cam; /* 0xf10 */
337 unsigned char res24[0x2c];
338 unsigned int clksel_cam; /* 0xf40 */
339 unsigned char res25[0xbc];
340 unsigned int fclken_per; /* 0x1000 */
341 unsigned char res26[0xc];
342 unsigned int iclken_per; /* 0x1010 */
343 unsigned char res27[0x2c];
344 unsigned int clksel_per; /* 0x1040 */
345 unsigned char res28[0xfc];
346 unsigned int clksel1_emu; /* 0x1140 */
348 #else /* __ASSEMBLY__ */
349 #define CM_CLKSEL_CORE 0x48004a40
350 #define CM_CLKSEL_GFX 0x48004b40
351 #define CM_CLKSEL_WKUP 0x48004c40
352 #define CM_CLKEN_PLL 0x48004d00
353 #define CM_CLKSEL1_PLL 0x48004d40
354 #define CM_CLKSEL1_EMU 0x48005140
355 #endif /* __ASSEMBLY__ */
357 #define PRM_BASE 0x48306000
361 unsigned char res1[0xd40];
362 unsigned int clksel; /* 0xd40 */
363 unsigned char res2[0x50c];
364 unsigned int rstctrl; /* 0x1250 */
365 unsigned char res3[0x1c];
366 unsigned int clksrc_ctrl; /* 0x1270 */
368 #else /* __ASSEMBLY__ */
369 #define PRM_RSTCTRL 0x48307250
370 #endif /* __ASSEMBLY__ */
372 #define SYSCLKDIV_1 (0x1 << 6)
373 #define SYSCLKDIV_2 (0x1 << 7)
375 #define CLKSEL_GPT1 (0x1 << 0)
377 #define EN_GPT1 (0x1 << 0)
378 #define EN_32KSYNC (0x1 << 2)
380 #define ST_WDT2 (0x1 << 5)
382 #define ST_MPU_CLK (0x1 << 0)
384 #define ST_CORE_CLK (0x1 << 0)
386 #define ST_PERIPH_CLK (0x1 << 1)
388 #define ST_IVA2_CLK (0x1 << 0)
390 #define RESETDONE (0x1 << 0)
392 #define TCLR_ST (0x1 << 0)
393 #define TCLR_AR (0x1 << 1)
394 #define TCLR_PRE (0x1 << 5)
397 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
398 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
399 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
400 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
404 unsigned char res1[0x48];
405 unsigned int req_info_permission_0; /* 0x48 */
406 unsigned char res2[0x4];
407 unsigned int read_permission_0; /* 0x50 */
408 unsigned char res3[0x4];
409 unsigned int wirte_permission_0; /* 0x58 */
410 unsigned char res4[0x4];
411 unsigned int addr_match_1; /* 0x58 */
412 unsigned char res5[0x4];
413 unsigned int req_info_permission_1; /* 0x68 */
414 unsigned char res6[0x14];
415 unsigned int addr_match_2; /* 0x80 */
417 #endif /*__ASSEMBLY__ */
419 /* Permission values for registers -Full fledged permissions to all */
420 #define UNLOCK_1 0xFFFFFFFF
421 #define UNLOCK_2 0x00000000
422 #define UNLOCK_3 0x0000FFFF
427 #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
428 #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
429 #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)