2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
29 #include <asm/types.h>
30 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
32 /* Register offsets of common modules */
34 #ifndef __KERNEL_STRICT_NAMES
38 u16 gpmc_nadv_ale; /* 0xC0 */
39 u16 gpmc_noe; /* 0xC2 */
40 u16 gpmc_nwe; /* 0xC4 */
42 u32 status; /* 0x2F0 */
43 u32 gpstatus; /* 0x2F4 */
45 u32 rpubkey_0; /* 0x300 */
46 u32 rpubkey_1; /* 0x304 */
47 u32 rpubkey_2; /* 0x308 */
48 u32 rpubkey_3; /* 0x30C */
49 u32 rpubkey_4; /* 0x310 */
51 u32 randkey_0; /* 0x318 */
52 u32 randkey_1; /* 0x31C */
53 u32 randkey_2; /* 0x320 */
54 u32 randkey_3; /* 0x324 */
56 u32 ctrl_omap_stat; /* 0x44C */
58 #else /* __ASSEMBLY__ */
59 #define CONTROL_STATUS 0x2F0
60 #endif /* __ASSEMBLY__ */
61 #endif /* __KERNEL_STRICT_NAMES */
64 #define OMAP3503 0x5c00
65 #define OMAP3515 0x1c00
66 #define OMAP3525 0x4c00
67 #define OMAP3530 0x0c00
69 #ifndef __KERNEL_STRICT_NAMES
73 u32 idcode; /* 0x04 */
74 u32 prod_id; /* 0x08 */
76 u32 die_id_0; /* 0x18 */
77 u32 die_id_1; /* 0x1C */
78 u32 die_id_2; /* 0x20 */
79 u32 die_id_3; /* 0x24 */
81 #endif /* __ASSEMBLY__ */
82 #endif /* __KERNEL_STRICT_NAMES */
85 #define DEVICE_MASK (0x7 << 8)
86 #define SYSBOOT_MASK 0x1F
87 #define TST_DEVICE 0x0
88 #define EMU_DEVICE 0x1
92 #define GPMC_BASE (OMAP34XX_GPMC_BASE)
93 #define GPMC_CONFIG_CS0 0x60
94 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
96 #ifndef __KERNEL_STRICT_NAMES
99 u32 config1; /* 0x00 */
100 u32 config2; /* 0x04 */
101 u32 config3; /* 0x08 */
102 u32 config4; /* 0x0C */
103 u32 config5; /* 0x10 */
104 u32 config6; /* 0x14 */
105 u32 config7; /* 0x18 */
106 u32 nand_cmd; /* 0x1C */
107 u32 nand_adr; /* 0x20 */
108 u32 nand_dat; /* 0x24 */
109 u8 res[8]; /* blow up to 0x30 byte */
114 u32 sysconfig; /* 0x10 */
116 u32 irqstatus; /* 0x18 */
117 u32 irqenable; /* 0x1C */
119 u32 timeout_control; /* 0x40 */
121 u32 config; /* 0x50 */
122 u32 status; /* 0x54 */
123 u8 res5[0x8]; /* 0x58 */
124 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
125 u8 res6[0x14]; /* 0x1E0 */
126 u32 ecc_config; /* 0x1F4 */
127 u32 ecc_control; /* 0x1F8 */
128 u32 ecc_size_config; /* 0x1FC */
129 u32 ecc1_result; /* 0x200 */
130 u32 ecc2_result; /* 0x204 */
131 u32 ecc3_result; /* 0x208 */
132 u32 ecc4_result; /* 0x20C */
133 u32 ecc5_result; /* 0x210 */
134 u32 ecc6_result; /* 0x214 */
135 u32 ecc7_result; /* 0x218 */
136 u32 ecc8_result; /* 0x21C */
137 u32 ecc9_result; /* 0x220 */
139 #else /* __ASSEMBLY__ */
140 #define GPMC_CONFIG1 0x00
141 #define GPMC_CONFIG2 0x04
142 #define GPMC_CONFIG3 0x08
143 #define GPMC_CONFIG4 0x0C
144 #define GPMC_CONFIG5 0x10
145 #define GPMC_CONFIG6 0x14
146 #define GPMC_CONFIG7 0x18
147 #endif /* __ASSEMBLY__ */
148 #endif /* __KERNEL_STRICT_NAMES */
151 #define FLASH_BASE 0x10000000 /* NOR flash, */
152 /* aligned to 256 Meg */
153 #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
154 /* aligned to 64 Meg */
155 #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
156 /* aligned to 256 Meg */
157 #define DEBUG_BASE 0x08000000 /* debug board */
158 #define NAND_BASE 0x30000000 /* NAND addr */
159 /* (actual size small port) */
160 #define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
161 #define ONENAND_MAP 0x20000000 /* OneNand addr */
162 /* (actual size small port) */
164 #ifndef __KERNEL_STRICT_NAMES
168 u32 sysconfig; /* 0x10 */
170 u32 rg_att0; /* 0x48 */
172 u32 class_arb0; /* 0xD0 */
174 #endif /* __ASSEMBLY__ */
175 #endif /* __KERNEL_STRICT_NAMES */
177 #define BURSTCOMPLETE_GROUP7 (0x1 << 31)
180 #ifndef __KERNEL_STRICT_NAMES
183 u32 mcfg; /* 0x80 || 0xB0 */
184 u32 mr; /* 0x84 || 0xB4 */
186 u32 emr2; /* 0x8C || 0xBC */
188 u32 rfr_ctrl; /* 0x84 || 0xD4 */
189 u32 manual; /* 0xA8 || 0xD8 */
194 u32 ctrla; /* 0x9C || 0xC4 */
195 u32 ctrlb; /* 0xA0 || 0xC8 */
200 u32 sysconfig; /* 0x10 */
201 u32 status; /* 0x14 */
203 u32 cs_cfg; /* 0x40 */
204 u32 sharing; /* 0x44 */
206 u32 dlla_ctrl; /* 0x60 */
207 u32 dlla_status; /* 0x64 */
208 u32 dllb_ctrl; /* 0x68 */
209 u32 dllb_status; /* 0x6C */
210 u32 power; /* 0x70 */
212 struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
214 #endif /* __ASSEMBLY__ */
215 #endif /* __KERNEL_STRICT_NAMES */
217 #define DLLPHASE_90 (0x1 << 1)
218 #define LOADDLL (0x1 << 2)
219 #define ENADLL (0x1 << 3)
220 #define DLL_DELAY_MASK 0xFF00
221 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
223 #define PAGEPOLICY_HIGH (0x1 << 0)
224 #define SRFRONRESET (0x1 << 7)
225 #define WAKEUPPROC (0x1 << 26)
227 #define DDR_SDRAM (0x1 << 0)
228 #define DEEPPD (0x1 << 3)
229 #define B32NOT16 (0x1 << 4)
230 #define BANKALLOCATION (0x2 << 6)
231 #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
232 #define ADDRMUXLEGACY (0x1 << 19)
233 #define CASWIDTH_10BITS (0x5 << 20)
234 #define RASWIDTH_13BITS (0x2 << 24)
235 #define BURSTLENGTH4 (0x2 << 0)
236 #define CASL3 (0x3 << 4)
237 #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
238 #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
239 #define ARE_ARCV_1 (0x1 << 0)
240 #define ARCV (0x4e2 << 8) /* Autorefresh count */
241 #define OMAP34XX_SDRC_CS0 0x80000000
242 #define OMAP34XX_SDRC_CS1 0xA0000000
244 #define CMD_PRECHARGE 0x1
245 #define CMD_AUTOREFRESH 0x2
246 #define CMD_ENTR_PWRDOWN 0x3
247 #define CMD_EXIT_PWRDOWN 0x4
248 #define CMD_ENTR_SRFRSH 0x5
249 #define CMD_CKE_HIGH 0x6
250 #define CMD_CKE_LOW 0x7
251 #define SOFTRESET (0x1 << 1)
252 #define SMART_IDLE (0x2 << 3)
253 #define REF_ON_IDLE (0x1 << 6)
255 /* timer regs offsets (32 bit regs) */
257 #ifndef __KERNEL_STRICT_NAMES
260 u32 tidr; /* 0x00 r */
262 u32 tiocp_cfg; /* 0x10 rw */
263 u32 tistat; /* 0x14 r */
264 u32 tisr; /* 0x18 rw */
265 u32 tier; /* 0x1c rw */
266 u32 twer; /* 0x20 rw */
267 u32 tclr; /* 0x24 rw */
268 u32 tcrr; /* 0x28 rw */
269 u32 tldr; /* 0x2c rw */
270 u32 ttgr; /* 0x30 rw */
271 u32 twpc; /* 0x34 r*/
272 u32 tmar; /* 0x38 rw*/
273 u32 tcar1; /* 0x3c r */
274 u32 tcicr; /* 0x40 rw */
275 u32 tcar2; /* 0x44 r */
277 #endif /* __ASSEMBLY__ */
278 #endif /* __KERNEL_STRICT_NAMES */
280 /* enable sys_clk NO-prescale /1 */
281 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
284 #ifndef __KERNEL_STRICT_NAMES
288 u32 wwps; /* 0x34 r */
290 u32 wspr; /* 0x48 rw */
292 #endif /* __ASSEMBLY__ */
293 #endif /* __KERNEL_STRICT_NAMES */
295 #define WD_UNLOCK1 0xAAAA
296 #define WD_UNLOCK2 0x5555
299 #define PRCM_BASE 0x48004000
301 #ifndef __KERNEL_STRICT_NAMES
304 u32 fclken_iva2; /* 0x00 */
305 u32 clken_pll_iva2; /* 0x04 */
307 u32 idlest_pll_iva2; /* 0x24 */
309 u32 clksel1_pll_iva2 ; /* 0x40 */
310 u32 clksel2_pll_iva2; /* 0x44 */
312 u32 clken_pll_mpu; /* 0x904 */
314 u32 idlest_pll_mpu; /* 0x924 */
316 u32 clksel1_pll_mpu; /* 0x940 */
317 u32 clksel2_pll_mpu; /* 0x944 */
319 u32 fclken1_core; /* 0xa00 */
321 u32 iclken1_core; /* 0xa10 */
322 u32 iclken2_core; /* 0xa14 */
324 u32 clksel_core; /* 0xa40 */
326 u32 fclken_gfx; /* 0xb00 */
328 u32 iclken_gfx; /* 0xb10 */
330 u32 clksel_gfx; /* 0xb40 */
332 u32 fclken_wkup; /* 0xc00 */
334 u32 iclken_wkup; /* 0xc10 */
336 u32 idlest_wkup; /* 0xc20 */
338 u32 clksel_wkup; /* 0xc40 */
340 u32 clken_pll; /* 0xd00 */
342 u32 idlest_ckgen; /* 0xd20 */
344 u32 clksel1_pll; /* 0xd40 */
345 u32 clksel2_pll; /* 0xd44 */
346 u32 clksel3_pll; /* 0xd48 */
348 u32 fclken_dss; /* 0xe00 */
350 u32 iclken_dss; /* 0xe10 */
352 u32 clksel_dss; /* 0xe40 */
354 u32 fclken_cam; /* 0xf00 */
356 u32 iclken_cam; /* 0xf10 */
358 u32 clksel_cam; /* 0xf40 */
360 u32 fclken_per; /* 0x1000 */
362 u32 iclken_per; /* 0x1010 */
364 u32 clksel_per; /* 0x1040 */
366 u32 clksel1_emu; /* 0x1140 */
368 #else /* __ASSEMBLY__ */
369 #define CM_CLKSEL_CORE 0x48004a40
370 #define CM_CLKSEL_GFX 0x48004b40
371 #define CM_CLKSEL_WKUP 0x48004c40
372 #define CM_CLKEN_PLL 0x48004d00
373 #define CM_CLKSEL1_PLL 0x48004d40
374 #define CM_CLKSEL1_EMU 0x48005140
375 #endif /* __ASSEMBLY__ */
376 #endif /* __KERNEL_STRICT_NAMES */
378 #define PRM_BASE 0x48306000
380 #ifndef __KERNEL_STRICT_NAMES
384 u32 clksel; /* 0xd40 */
386 u32 rstctrl; /* 0x1250 */
388 u32 clksrc_ctrl; /* 0x1270 */
390 #else /* __ASSEMBLY__ */
391 #define PRM_RSTCTRL 0x48307250
392 #endif /* __ASSEMBLY__ */
393 #endif /* __KERNEL_STRICT_NAMES */
395 #define SYSCLKDIV_1 (0x1 << 6)
396 #define SYSCLKDIV_2 (0x1 << 7)
398 #define CLKSEL_GPT1 (0x1 << 0)
400 #define EN_GPT1 (0x1 << 0)
401 #define EN_32KSYNC (0x1 << 2)
403 #define ST_WDT2 (0x1 << 5)
405 #define ST_MPU_CLK (0x1 << 0)
407 #define ST_CORE_CLK (0x1 << 0)
409 #define ST_PERIPH_CLK (0x1 << 1)
411 #define ST_IVA2_CLK (0x1 << 0)
413 #define RESETDONE (0x1 << 0)
415 #define TCLR_ST (0x1 << 0)
416 #define TCLR_AR (0x1 << 1)
417 #define TCLR_PRE (0x1 << 5)
420 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
421 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
422 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
423 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
425 #ifndef __KERNEL_STRICT_NAMES
429 u32 req_info_permission_0; /* 0x48 */
431 u32 read_permission_0; /* 0x50 */
433 u32 wirte_permission_0; /* 0x58 */
435 u32 addr_match_1; /* 0x58 */
437 u32 req_info_permission_1; /* 0x68 */
439 u32 addr_match_2; /* 0x80 */
441 #endif /*__ASSEMBLY__ */
442 #endif /* __KERNEL_STRICT_NAMES */
444 /* Permission values for registers -Full fledged permissions to all */
445 #define UNLOCK_1 0xFFFFFFFF
446 #define UNLOCK_2 0x00000000
447 #define UNLOCK_3 0x0000FFFF
452 #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
453 #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
454 #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)