2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
38 #endif /* __ASSEMBLY__ */
42 /* Slower full frequency range default timings for x32 operation*/
43 #define SDP_SDRC_SHARING 0x00000100
44 #define SDP_SDRC_MR_0_SDR 0x00000031
46 /* optimized timings good for current shipping parts */
47 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
50 #define DLL_WRITEDDRCLKX2DIS 1
53 #define DLL_DLLPHASE_72 0
54 #define DLL_DLLPHASE_90 1
56 /* rkw - need to find of 90/72 degree recommendation for speed like before */
57 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
58 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
60 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns
62 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
63 * TDPL (Twr) = 15/6 = 2.5 -> 3
82 #define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
83 (TRAS_165 << 18) | (TRP_165 << 15) | \
84 (TRCD_165 << 12) | (TRRD_165 << 9) | \
85 (TDPL_165 << 6) | (TDAL_165))
91 #define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
92 (TXP_165 << 8) | (TWTR_165 << 16))
94 #define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
95 #define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
96 #define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
100 * Definitions is as per the following format
101 * #define <PART>_GPMC_CONFIG<x> <value>
103 * PART is the part name e.g. STNOR - Intel Strata Flash
104 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
105 * Value is corresponding value
107 * For every valid PRCM configuration there should be only one definition of
108 * the same. if values are independent of the board, this definition will be
109 * present in this file if values are dependent on the board, then this should
110 * go into corresponding mem-boardName.h file
112 * Currently valid part Names are (PART):
113 * STNOR - Intel Strata Flash
114 * SMNAND - Samsung NAND
115 * MPDB - H4 MPDB board
117 * MNAND - Micron Large page x16 NAND
118 * ONNAND - Samsung One NAND
120 * include/configs/file.h contains the defn - for all CS we are interested
121 * #define OMAP34XX_GPMC_CSx PART
122 * #define OMAP34XX_GPMC_CSx_SIZE Size
123 * #define OMAP34XX_GPMC_CSx_MAP Map
126 * PART - Part Name as defined above
127 * SIZE - how big is the mapping to be
128 * GPMC_SIZE_128M - 0x8
129 * GPMC_SIZE_64M - 0xC
130 * GPMC_SIZE_32M - 0xE
131 * GPMC_SIZE_16M - 0xF
132 * MAP - Map this CS to which address(GPMC address space)- Absolute address
133 * >>24 before being used.
135 #define GPMC_SIZE_128M 0x8
136 #define GPMC_SIZE_64M 0xC
137 #define GPMC_SIZE_32M 0xE
138 #define GPMC_SIZE_16M 0xF
140 #define SMNAND_GPMC_CONFIG1 0x00000800
141 #define SMNAND_GPMC_CONFIG2 0x00141400
142 #define SMNAND_GPMC_CONFIG3 0x00141400
143 #define SMNAND_GPMC_CONFIG4 0x0F010F01
144 #define SMNAND_GPMC_CONFIG5 0x010C1414
145 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80
146 #define SMNAND_GPMC_CONFIG7 0x00000C44
148 #define M_NAND_GPMC_CONFIG1 0x00001800
149 #define M_NAND_GPMC_CONFIG2 0x00141400
150 #define M_NAND_GPMC_CONFIG3 0x00141400
151 #define M_NAND_GPMC_CONFIG4 0x0F010F01
152 #define M_NAND_GPMC_CONFIG5 0x010C1414
153 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80
154 #define M_NAND_GPMC_CONFIG7 0x00000C44
156 #define STNOR_GPMC_CONFIG1 0x3
157 #define STNOR_GPMC_CONFIG2 0x00151501
158 #define STNOR_GPMC_CONFIG3 0x00060602
159 #define STNOR_GPMC_CONFIG4 0x11091109
160 #define STNOR_GPMC_CONFIG5 0x01141F1F
161 #define STNOR_GPMC_CONFIG6 0x000004c4
163 #define SIBNOR_GPMC_CONFIG1 0x1200
164 #define SIBNOR_GPMC_CONFIG2 0x001f1f00
165 #define SIBNOR_GPMC_CONFIG3 0x00080802
166 #define SIBNOR_GPMC_CONFIG4 0x1C091C09
167 #define SIBNOR_GPMC_CONFIG5 0x01131F1F
168 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
170 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
171 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
172 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
173 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
174 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
175 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
177 #define MPDB_GPMC_CONFIG1 0x00011000
178 #define MPDB_GPMC_CONFIG2 0x001f1f01
179 #define MPDB_GPMC_CONFIG3 0x00080803
180 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a
181 #define MPDB_GPMC_CONFIG5 0x041f1F1F
182 #define MPDB_GPMC_CONFIG6 0x1F0F04C4
184 #define P2_GPMC_CONFIG1 0x0
185 #define P2_GPMC_CONFIG2 0x0
186 #define P2_GPMC_CONFIG3 0x0
187 #define P2_GPMC_CONFIG4 0x0
188 #define P2_GPMC_CONFIG5 0x0
189 #define P2_GPMC_CONFIG6 0x0
191 #define ONENAND_GPMC_CONFIG1 0x00001200
192 #define ONENAND_GPMC_CONFIG2 0x000F0F01
193 #define ONENAND_GPMC_CONFIG3 0x00030301
194 #define ONENAND_GPMC_CONFIG4 0x0F040F04
195 #define ONENAND_GPMC_CONFIG5 0x010F1010
196 #define ONENAND_GPMC_CONFIG6 0x1F060000
198 #define NET_GPMC_CONFIG1 0x00001000
199 #define NET_GPMC_CONFIG2 0x001e1e01
200 #define NET_GPMC_CONFIG3 0x00080300
201 #define NET_GPMC_CONFIG4 0x1c091c09
202 #define NET_GPMC_CONFIG5 0x04181f1f
203 #define NET_GPMC_CONFIG6 0x00000FCF
204 #define NET_GPMC_CONFIG7 0x00000f6c
206 /* max number of GPMC Chip Selects */
207 #define GPMC_MAX_CS 8
208 /* max number of GPMC regs */
209 #define GPMC_MAX_REG 7
212 #define PISMO1_NAND 2
215 #define PISMO1_ONENAND 5
217 #define PISMO2_NAND_CS0 7
218 #define PISMO2_NAND_CS1 8
220 /* make it readable for the gpmc_init */
221 #define PISMO1_NOR_BASE FLASH_BASE
222 #define PISMO1_NAND_BASE NAND_BASE
223 #define PISMO2_CS0_BASE PISMO2_MAP1
224 #define PISMO1_ONEN_BASE ONENAND_MAP
225 #define DBG_MPDB_BASE DEBUG_BASE
227 #endif /* endif _MEM_H_ */